公开(公告)号：US06425110B1

公开(公告)日：2002-07-23

申请号：US09213675

申请日：1998-12-17

申请人： David J. Hathaway ,  Anthony D. Drumm ,  Peter J. Osler

发明人： David J. Hathaway ,  Anthony D. Drumm ,  Peter J. Osler

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method for analyzing and optimizing a design, such as a circuit design, which relates to the application of at least one optimization procedure, evaluating the benefit and net cost of the optimization procedure and then through the checkpoint manager, recording and reversing changes of the design. The execution and reversal of multiple optimizations may occur in a trial mode followed by evaluation of the executed and reversed designs and then the reinstatement of the best optimization.

摘要翻译： 一种用于分析和优化诸如电路设计的设计的方法，其涉及应用至少一个优化过程，评估优化过程的益处和净成本，然后通过检查点管理器，记录和反转变化 设计。 多个优化的执行和反转可能发生在试用模式中，之后是执行和反向设计的评估，然后恢复最佳优化。

公开(公告)号：US06588000B2

公开(公告)日：2003-07-01

申请号：US09682248

申请日：2001-08-09

申请人： Paul T. Gutwin ,  Peter J. Osler

发明人： Paul T. Gutwin ,  Peter J. Osler

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level. The method comprises the steps of identifying a desired number of blocks for the second hierarchical level, representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary, and identifying transistor networks that extend across block boundaries. The method further comprises the steps of assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and re-assigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block. Preferably, the transistors are assigned from one block to another by identifying partitions for groups of transistors; and then reassigning assigning transistors on the basis of said partitions. For example, the transistors may be partitioned on the basis of functionality, by name, to minimize connectivity, or to duplicate pre-existing hierarchy.

公开(公告)号：US08495547B2

公开(公告)日：2013-07-23

申请号：US12910336

申请日：2010-10-22

申请人： Joachim Keinert ,  Douglass T. Lamb ,  Peter J. Osler

发明人： Joachim Keinert ,  Douglass T. Lamb ,  Peter J. Osler

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated.

摘要翻译： 集成电路（IC）设计，具有多个含有需要二次电源的电池的金属层。 在将主电源/接地网格的电池和条纹放置在IC设计的金属层中之后，特定电池在第一金属层中设置有次级电源条。 次级功率条纹被设计成使得每个次级电源/接地条带与不同金属层中的对应的主电源/接地网格的条带完全重叠。 随后，来自IC设计的信号被路由，并且产生主电源/接地网格条和次级电源/接地条之间的电源通孔。

公开(公告)号：US20110113398A1

公开(公告)日：2011-05-12

申请号：US12910336

申请日：2010-10-22

申请人： Joachim Keinert ,  Douglass T. Lamb ,  Peter J. Osler

发明人： Joachim Keinert ,  Douglass T. Lamb ,  Peter J. Osler

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated.

摘要翻译： 集成电路（IC）设计，具有多个含有需要二次电源的电池的金属层。 在将主电源/接地网格的电池和条纹放置在IC设计的金属层中之后，特定电池在第一金属层中设置有次级电源条。 次级功率条纹被设计成使得每个次级电源/接地条带与不同金属层中的对应的主电源/接地网格的条带完全重叠。 随后，来自IC设计的信号被路由，并且产生主电源/接地网格条和次级电源/接地条之间的电源通孔。

公开(公告)号：US06829755B2

公开(公告)日：2004-12-07

申请号：US09682294

申请日：2001-08-16

申请人： Paul T. Gutwin ,  Peter J. Osler

发明人： Paul T. Gutwin ,  Peter J. Osler

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.

摘要翻译： 一种用于专用型集成电路（ASIC）的静态时序分析的方法和系统。 该方法包括使用晶体管电平定时（TLT）方法，仅在定时图生成期间检测到开放通道电路输入时才使用。

公开(公告)号：US5099415A

公开(公告)日：1992-03-24

申请号：US311666

申请日：1989-02-15

申请人： Peter J. Osler ,  Fred T. Tong

发明人： Peter J. Osler ,  Fred T. Tong

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1027

摘要： A system providing a guess mechanism for improving the speed of translating effective addresses produced by a processor to real addresses in memory is disclosed wherein a set of Lookaside Tables and logic elements are used along with a set of validity registers and an MRU register to guess at the appropriate real frame index from one of the Tables to be output in the real address in the first cycle of a two cycle operation. The low order bits of the effective address are sent to index the Tables during the first cycle and the high order bits are used during the second cycle for comparison with the set of Table entries selected in the first cycle as containing the real frame index that is output. The selection of the actual real frame index that is output involves a guess using the validity and MRU registers along with indexing of the Tables by a portion of the low order bits. If the logic indicates, upon comparison of 1) the Table entry containing the real frame index that is output during the first cycle with 2) the high order bit comparison of the second cycle, that the selected real frame index was inappropriate, a signal is sent after the second cycle to invalidate the output of the real address incorporating that real frame index.