公开(公告)号：US06226722B1

公开(公告)日：2001-05-01

申请号：US08245786

申请日：1994-05-19

Applicant: David James Shippy ,  David Benjamin Shuler

Inventor： David James Shippy ,  David Benjamin Shuler

IPC: G06F1208

CPC classification number: G06F12/0884 ,  G06F12/0897

Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

Abstract translation: 一种存储器系统，其中数据检索同时在二级高速缓存和主存储器中启动，这允许与仲裁相关联的存储器延迟，存储器DRAM地址转换等在处理器寻求的数据不在的情况下被最小化 L2缓存（miss）。 本发明允许任何存储器访问在任何存储器信号被激活之前在存储控制单元中中断。 L2和存储器访问控制在单个组件中，即存储控制单元（SCU）。 L2和存储器都有一个独特的CPU端口，允许直接传输数据。 这消除了将数据存储在诸如高速缓存或存储器控制器的中间设备中的开销。