公开(公告)号：US06654876B1

公开(公告)日：2003-11-25

申请号：US09434875

申请日：1999-11-04

Applicant: Hung Qui Le ,  David James Shippy

Inventor： Hung Qui Le ,  David James Shippy

IPC: G06F930

CPC classification number: G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3865

Abstract: A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle. In one embodiment, the number of cycles between the first cycle and the determination cycle includes the number of cycles required to travel a pipeline of the microprocessor plus the number of cycles indicated by the delay value.

Abstract translation: 公开了一种实现延迟拒绝机制的方法，处理器和数据处理系统。 该处理器包括适于在第一周期中发出指令的发布单元和负载存储单元（LSU）。 LSU包括扩展拒绝计算器电路，被配置为接收一组完成信息信号并基于此生成延迟值。 LSU适于确定是否在确定周期中拒绝该指令。 第一周期和确定周期之间的周期数是延迟值的函数，使得拒绝定时相对于第一周期是可变的。 在一个实施例中，处理器还被配置为在确定周期之后重新发出指令，如果指令在确定周期中被拒绝。 在一个实施例中，延迟值通过2位总线传送。 2位总线允许在完成循环后将判定周期从0到3个周期延迟。 在一个实施例中，第一周期和确定周期之间的循环次数包括行进微处理器的流水线所需的循环次数加上由延迟值指示的周期数。

公开(公告)号：US06490653B1

公开(公告)日：2002-12-03

申请号：US09325397

申请日：1999-06-03

Applicant: Robert Alan Cargnoni ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

Inventor： Robert Alan Cargnoni ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

IPC: G06F1208

CPC classification number: G06F9/383 ,  G06F9/3842

Abstract: A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles. In an embodiment, a core interface unit (CIU) will signal an execution unit such as the Load Store Unit (LSU) that it is assumed that the instruction will hit in the L2 cache. An issue queue uses the signal to issue dependent instructions at an optimal time. If the instruction misses in the L2 cache, the cache hierarchy causes the instructions to be abandoned and re-executed when the data is available.

Abstract translation: 公开了一种用于最佳地发出与数据处理系统中的第一指令相关的指令的方法。 处理系统包括主缓存和二级缓存。 所述方法和系统包括推测性地指示二次高速缓存中的第一指令的命中并释放依赖指令。 该方法和系统包括确定第一指令是否在二级高速缓存内。 所述方法和系统还包括当所述指令在所述辅助高速缓存内时，将与所述第二指令相关的数据提供给所述主缓存。 根据本发明的方法和系统预先产生依赖性（诸如加载指令）的指令来发送发出队列（其负责发出具有解决的冲突的指令），指令将以预定数量完成 的周期。 在一个实施例中，核心接口单元（CIU）将向诸如加载存储单元（LSU）的执行单元发出信号，假定该指令将在L2高速缓存中命中。 问题队列使用信号在最佳时间发出相关指令。 如果L2缓存中的指令丢失，则缓存层次结构会导致在数据可用时放弃指令并重新执行指令。

公开(公告)号：US06349382B1

公开(公告)日：2002-02-19

申请号：US09263665

申请日：1999-03-05

Applicant: Kurt Alan Feiste ,  Bruce Joseph Ronchetti ,  David James Shippy

Inventor： Kurt Alan Feiste ,  Bruce Joseph Ronchetti ,  David James Shippy

IPC: G06F1500

CPC classification number: G06F9/3834 ,  G06F9/3824

Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.

Abstract translation: 在微处理器内的加载/存储单元中，加载和存储指令是无序执行的。 加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。 当执行加载指令时，确定加载指令是否试图将数据加载到与先前执行的存储指令正在等待完成的存储单元相同的存储单元。 如果是这样，则通过存储指令等待存储在高速缓存内的数据被直接转发到加载指令。

公开(公告)号：US06543002B1

公开(公告)日：2003-04-01

申请号：US09435066

申请日：1999-11-04

Applicant: James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

Inventor： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

IPC: G06F1100

CPC classification number: G06F11/0721 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/0793 ,  G06F11/1405

Abstract: A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch. The hang recovery unit then asserts a force reject signal to an execution unit to reject all instructions pending in the execution unit's pipeline and a flush signal to the execution unit that results in the processor flushing a set of instructions. The hang recovery unit then negates the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.

公开(公告)号：US06298436B1

公开(公告)日：2001-10-02

申请号：US09327644

申请日：1999-06-08

Applicant: James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

Inventor： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

IPC: G06F9305

CPC classification number: G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3842

Abstract: A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.

Abstract translation: 一种用于处理器系统中的原子存储器访问的方法和系统，其中所述处理器系统能够相对于特定程序顺序发出并执行不正常的多个指令。 推测性地向处理器系统的执行单元发出第一预约指令。 在发行时，响应于在程序中的第一预约指令之后发生的执行单元中检测到任何先前执行的预定指令而从执行单元中刷新在程序顺序中的第一预约指令之后发生的执行单元排队的指令 订购。 响应于在程序顺序中的第一预约指令之前发生的执行单元排队的指令的完成，通过对第一预约指令的特定数据地址进行预约来推测地执行第一预约指令，使得预约指令 相对于合作条件存储指令，以任何顺序被推测地发行和执行的这些被按顺序执行。

公开(公告)号：US06237081B1

公开(公告)日：2001-05-22

申请号：US09213319

申请日：1998-12-16

Applicant: Hung Qui Le ,  Larry Edward Thatcher ,  Bruce Joseph Ronchetti ,  David James Shippy

Inventor： Hung Qui Le ,  Larry Edward Thatcher ,  Bruce Joseph Ronchetti ,  David James Shippy

IPC: G06F932

CPC classification number: G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3861

Abstract: A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.

Abstract translation: 处理器（100）包括具有用于向执行单元（140）发出指令的发布队列（144）的发布单元（125）。 执行单元（140）可接受并执行该指令或产生拒绝信号。 在发出每条指令之后，发出队列（144）保留发出的关键周期指令。 在关键时段之后，发布队列（144）可以放弃发出的指令，除非执行单元（140）已经产生了拒绝信号。 如果执行单元（140）已经产生了拒绝信号，则指令最终在发布队列（144）中被标记为可重新发行。 可以根据执行单元（140）的拒绝的性质来修改拒绝指令从重新发行保持的时间长度。 此外，执行单元（140）可以响应于某些拒绝条件进行校正动作，使得可以在重新发布时完全执行该指令。

公开(公告)号：US06226722B1

公开(公告)日：2001-05-01

申请号：US08245786

申请日：1994-05-19

Applicant: David James Shippy ,  David Benjamin Shuler

Inventor： David James Shippy ,  David Benjamin Shuler

IPC: G06F1208

CPC classification number: G06F12/0884 ,  G06F12/0897

Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.

Abstract translation: 一种存储器系统，其中数据检索同时在二级高速缓存和主存储器中启动，这允许与仲裁相关联的存储器延迟，存储器DRAM地址转换等在处理器寻求的数据不在的情况下被最小化 L2缓存（miss）。 本发明允许任何存储器访问在任何存储器信号被激活之前在存储控制单元中中断。 L2和存储器访问控制在单个组件中，即存储控制单元（SCU）。 L2和存储器都有一个独特的CPU端口，允许直接传输数据。 这消除了将数据存储在诸如高速缓存或存储器控制器的中间设备中的开销。

公开(公告)号：US06658555B1

公开(公告)日：2003-12-02

申请号：US09435077

申请日：1999-11-04

Applicant: James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

Inventor： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

IPC: G06F930

CPC classification number: G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3885

Abstract: A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

公开(公告)号：US06336183B1

公开(公告)日：2002-01-01

申请号：US09259140

申请日：1999-02-26

Applicant: Hung Qui Le ,  Robert Greg McDonald ,  David James Shippy ,  Larry Edward Thatcher

Inventor： Hung Qui Le ,  Robert Greg McDonald ,  David James Shippy ,  Larry Edward Thatcher

IPC: G06F9312

CPC classification number: G06F9/3889 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

Abstract: In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

Abstract translation: 在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。 存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。 如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。 如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

公开(公告)号：US06336168B1

公开(公告)日：2002-01-01

申请号：US09259139

申请日：1999-02-26

Applicant: Marlin Wayne Frederick, Jr. ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

Inventor： Marlin Wayne Frederick, Jr. ,  Bruce Joseph Ronchetti ,  David James Shippy ,  Larry Edward Thatcher

IPC: G06F1316

CPC classification number: G06F9/30043 ,  G06F9/3824

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract translation: 在加载存储单元中执行多个加载指令的流水线和并行执行。 当第一个加载指令引起高速缓存未命中并继续从系统存储器层次结构检索加载数据时，寻址相同加载数据的第二加载指令将被合并到第一加载指令中，以便从系统内存层次结构返回的数据为 发送到注册与第一和第二加载指令相关联的文件。 结果，第二加载指令不必等待，直到在数据高速缓存中写入和验证加载数据。