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公开(公告)号：US20130111000A1
公开(公告)日：2013-05-02
申请号：US13285773
申请日：2011-10-31
IPC分类号： G06F15/173
CPC分类号： G06F9/5083 , G06F9/4881 , G06F9/50 , H04L49/90
摘要： A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. A pointer is added to the list based on an indication of whether the associated processor accepts the WQE corresponding to the pointer.
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公开(公告)号：US09059945B2
公开(公告)日：2015-06-16
申请号：US13285773
申请日：2011-10-31
IPC分类号： G06F9/46 , H04L12/861 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5083 , G06F9/4881 , G06F9/50 , H04L49/90
摘要： A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. A pointer is added to the list based on an indication of whether the associated processor accepts the WQE corresponding to the pointer.
摘要翻译： 网络处理器包括用于将工作调度和分配给多个处理器的调度，同步和顺序（SSO）模块。 SSO包括提供具有多个条目的表的每个单元（ODU），每个条目存储相应的工作队列条目和多个列表。 每个列表可以与被配置为执行工作的相应处理器相关联，并且包括指向表中条目的指针。 基于关联处理器是否接受与指针相对应的WQE的指示，将指针添加到列表中。
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公开(公告)号：US06624663B2
公开(公告)日：2003-09-23
申请号：US10000258
申请日：2001-10-31
IPC分类号： H03K301
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/78609 , H03K19/0016 , H03K19/00384
摘要： A clock driver is disclosed that minimizes propagation delay, and thus improves the integrity of a clock distribution network. The clock driver preferably is implemented with silicon-on-insulator (SOI) technology, and comprises an inverter with an nFET and pFET that are body-connected. The body connection serves to reduce the body voltage of the pFET, while increasing the body voltage of the nFET. This shifting of the voltage reduces the voltage threshold differential for both the nFET and pFET, which translates into a design that experiences less propagation delay due to voltage variations and fluctuations. If desired, the body voltages may be slightly offset from each other by placing one or more voltage drop transistors in the conductive path between the bodies of the nFET and pFET. In addition, the present invention may be used to design a programmable inverter that can operate in a low power mode, or in a high precision mode.
摘要翻译： 公开了一种使传播延迟最小化的时钟驱动器，从而提高了时钟分配网络的完整性。 时钟驱动器优选地采用绝缘体上硅（SOI）技术实现，并且包括具有体电连接的nFET和pFET的反相器。 身体连接用于降低pFET的体电压，同时增加nFET的体电压。 电压的这种移动降低了nFET和pFET两者的电压阈值差，这转化为由于电压变化和波动而经历较少传播延迟的设计。 如果需要，通过在nFET和pFET的主体之间的导电路径中放置一个或多个压降晶体管，体电压可以彼此稍微偏移。 此外，本发明可以用于设计可以以低功率模式或高精度模式操作的可编程逆变器。
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