公开(公告)号：US07742265B2

公开(公告)日：2010-06-22

申请号：US11145903

申请日：2005-06-06

Applicant: David R. Rice

Inventor： David R. Rice

IPC: H02H9/00

CPC classification number: H01L27/0266

Abstract: In one embodiment, an ESD protection circuit comprises a switchable current sinking circuit connected to a positive ESD clamp rail voltage, which may be a power supply voltage, and a single trigger control circuit coupled to a control connection of the switchable current sinking circuit. The single trigger control circuit may be configured to couple the control connection of the switchable current sinking circuit to a negative ESD clamp rail voltage, which may be signal ground, during an ESD event occurring on the positive ESD clamp rail connection. In one embodiment, the switchable current sinking circuit is capable of sinking large amounts of current, and the ESD protection circuit is tolerant of rail voltages that exceed the breakdown voltage of semiconductor devices used in constructing the ESD circuit. In one embodiment, the single trigger control circuit is implemented with a single n-well, thereby minimizing the amount of required silicon area during fabrication of the ESD protection circuit.

Abstract translation: 在一个实施例中，ESD保护电路包括连接到正ESD钳位电压的可切换电流吸收电路，其可以是电源电压，以及耦合到可切换电流吸收电路的控制连接的单个触发控制电路。 单个触发控制电路可以被配置为在ESD ESD钳位导轨连接处发生ESD事件期间将可切换电流吸收电路的控制连接耦合到可能被信号接地的负ESD钳位电压。 在一个实施例中，可切换电流吸收电路能够吸收大量的电流，并且ESD保护电路容许超过用于构建ESD电路的半导体器件的击穿电压的轨电压。 在一个实施例中，单个触发控制电路由单个n阱实现，由此在ESD保护电路的制造期间最小化所需的硅面积的量。

公开(公告)号：US5396553A

公开(公告)日：1995-03-07

申请号：US84040

申请日：1993-06-28

Applicant: Lance J. Haughton ,  David R. Rice

Inventor： Lance J. Haughton ,  David R. Rice

IPC: H04Q1/54 ,  H04M3/40 ,  H04Q3/42 ,  H04M1/00 ,  H04M7/04

CPC classification number: H04M3/40

Abstract: Disclosed is a circuit for providing an appropriate amount of on-hook loss in a digital loop carder transmission system serving telephone customers. The resistance of the customer loop is measured while the customer is off-hook and an amount of loss is added based on that resistance during the off-hook interval. A predetermined constant loss is then added to the appropriate off-hook loss when the equipment returns to on-hook status.

Abstract translation: 公开了一种在为电话客户服务的数字环路卡器传输系统中提供适当数量的挂机损耗的电路。 在客户摘机时测量客户回路的阻力，并且在摘机间隔期间基于该阻力添加损失量。 然后，当设备返回到挂机状态时，将预定的恒定损耗加到适当的摘机损失。

公开(公告)号：US20080165459A1

公开(公告)日：2008-07-10

申请号：US11621724

申请日：2007-01-10

Applicant: Patrick J. Holly ,  David Rodriguez ,  David R. Rice

Inventor： Patrick J. Holly ,  David Rodriguez ,  David R. Rice

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

Abstract translation: 系统，例如 集成电路或部件可以包括多个焊盘，例如， 数字I / O焊盘，每个包括物理焊盘和相关焊盘电路。 在影响一个或多个数字I / O焊盘的ESD事件的情况下，配置在I / O焊盘电源轨和物理输出焊盘之间的输出缓冲区中的PMOS器件在受影响的数字I的各自的焊盘电路内 / O焊盘 - 可能会响应于ESD事件而打开。 这可以允许每个焊盘的电容，在一些情况下，每个焊盘约为3pF的电容充电，吸收ESD事件的能量并降低集成电路或部件作为ESD事件的结果所经历的峰值电压。 降低的峰值电压可以直接与产品的ESD性能相关。

公开(公告)号：US07564665B2

公开(公告)日：2009-07-21

申请号：US11621724

申请日：2007-01-10

Applicant: Patrick J. Holly ,  David Rodriguez ,  David R. Rice

Inventor： Patrick J. Holly ,  David Rodriguez ,  David R. Rice

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

Abstract translation: 系统，例如 集成电路或部件可以包括多个焊盘，例如， 数字I / O焊盘，每个包括物理焊盘和相关焊盘电路。 在影响一个或多个数字I / O焊盘的ESD事件的情况下，配置在I / O焊盘电源轨和物理输出焊盘之间的输出缓冲区中的PMOS器件在其受影响的数字I的各自的焊盘电路内 / O焊盘 - 可能会响应于ESD事件而打开。 这可以允许每个焊盘的电容，在一些情况下，每个焊盘约为3pF的电容充电，吸收ESD事件的能量并降低集成电路或部件作为ESD事件的结果所经历的峰值电压。 降低的峰值电压可以直接与产品的ESD性能相关。