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1.发明授权公开(公告)号：US08949549B2
公开(公告)日：2015-02-03
申请号：US12324628
申请日：2008-11-26
CPC分类号： G06F9/526 , G06F3/067 , G06F12/0813
摘要： A method to exchange data in a shared memory system includes the use of a buffer in communication with a producer processor and a consumer processor. The cache data is temporarily stored in the buffer. The method includes for the consumer and the producer to indicate intent to acquire ownership of the buffer. In response to the indication of intent, the producer, consumer, buffer are prepared for the access. If the consumer intends to acquire the buffer, the producer places the cache data into the buffer. If the producer intends to acquire the buffer, the consumer removes the cache data from the buffer. The access to the buffer, however, is delayed until the producer, consumer, and the buffer are prepared.
摘要翻译： 在共享存储器系统中交换数据的方法包括使用与生产者处理器和消费者处理器进行通信的缓冲器。 高速缓存数据临时存储在缓冲区中。 该方法包括为消费者和生产者指示获取缓冲器所有权的意图。 响应于意图的指示，生产者，消费者，缓冲区准备进行访问。 如果消费者想要获取缓冲区，生产者将缓存数据放入缓冲区。 如果生产者打算获取缓冲区，消费者将从缓冲区中删除缓存数据。 然而，缓冲区的访问被延迟，直到生产者，消费者和缓冲区被准备好。
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2.发明申请公开(公告)号：US20100131720A1
公开(公告)日：2010-05-27
申请号：US12324628
申请日：2008-11-26
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F3/067 , G06F12/0813
摘要： A method to exchange data in a shared memory system includes the use of a buffer in communication with a producer processor and a consumer processor. The cache data is temporarily stored in the buffer. The method includes for the consumer and the producer to indicate intent to acquire ownership of the buffer. In response to the indication of intent, the producer, consumer, buffer are prepared for the access. If the consumer intends to acquire the buffer, the producer places the cache data into the buffer. If the producer intends to acquire the buffer, the consumer removes the cache data from the buffer. The access to the buffer, however, is delayed until the producer, consumer, and the buffer are prepared.
摘要翻译： 在共享存储器系统中交换数据的方法包括使用与生产者处理器和消费者处理器进行通信的缓冲器。 高速缓存数据临时存储在缓冲区中。 该方法包括为消费者和生产者指示获取缓冲器所有权的意图。 响应于意图的指示，生产者，消费者，缓冲区准备进行访问。 如果消费者想要获取缓冲区，生产者将缓存数据放入缓冲区。 如果生产者打算获取缓冲区，消费者将从缓冲区中删除缓存数据。 然而，缓冲区的访问被延迟，直到生产者，消费者和缓冲区被准备好。
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公开(公告)号：US20110243074A1
公开(公告)日：2011-10-06
申请号：US12753913
申请日：2010-04-05
CPC分类号： H04L47/70 , H04B10/1149 , H04B10/803 , H04L12/6402 , H04L41/12 , H04L47/50 , H04L49/25
摘要： A data center includes a plurality of computing units that communicate with each other using wireless communication, such as high frequency RF wireless communication. The data center may organize the computing units into groups (e.g., racks). In one implementation, each group may form a three-dimensional structure, such as a column having a free-space region for accommodating intra-group communication among computing units. The data center can include a number of features to facilitate communication, including dual-use memory for handling computing and buffering tasks, failsafe routing mechanisms, provisions to address permanent interface and hidden terminal scenarios, etc.
摘要翻译： 数据中心包括使用诸如高频RF无线通信之类的无线通信彼此通信的多个计算单元。 数据中心可以将计算单元组织成组（例如，机架）。 在一个实现中，每个组可以形成三维结构，诸如具有用于容纳计算单元之间的组内通信的自由空间区域的列。 数据中心可以包括一些便于通信的功能，包括用于处理计算和缓冲任务的双重使用内存，故障安全路由机制，解决永久接口和隐藏终端场景的规定等。
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公开(公告)号：US4918600A
公开(公告)日：1990-04-17
申请号：US226721
申请日：1988-08-01
CPC分类号： G06F12/0607 , G06F12/0207
摘要： Conflict-free vector access of any constant stride is made by preselecting a storage scheme for each vector based on the accessing patterns to be used with that vector. A respective storage scheme for each vector, for example, is selected to provide conflict-free access for a predetermined stride S. The respective storage scheme involves a rotation or permutation of an addressed row of corresponding memory locations in N parallel modules in main memory. The amount of rotation or permutation is a predetermined function of the predetermined stride S and the row address. The rotation is performed by modulo-N addition, or the permutation is performed by a set of exclusive-OR gates. For a system in which N is a power of 2 such that n=log.sub.2 N, the predetermined stride S is factored into an odd component and an even component that is a power of 2. The factorization is easily performed by a shift and count procedure, a shifter and counter, or a priority encoder. The amount of rotation or permutation is a predetermined function of the even component and the row address, and is preferably obtained by selecting a field of the row address in accordance with the maximum of s and n, and masking the selected field with a mask generated from the minimum of s and n.
摘要翻译： 基于与该向量一起使用的访问模式，通过预选每个向量的存储方案来进行任何恒定步长的无冲突向量访问。 例如，针对每个向量的相应存储方案被选择以提供对于预定步幅S的无冲突访问。相应的存储方案涉及在主存储器中的N个并行模块中的对应存储器位置的寻址行的旋转或置换。 旋转或置换的量是预定步幅S和行地址的预定函数。 通过模N加法执行旋转，或者由一组异或门执行置换。 对于其中N是2的幂的系统，使得n = log2N，将预定步幅S分解为奇数分量，即2的幂的偶数分量。因子分解易于通过移位和计数过程执行， 移位器和计数器，或优先编码器。 旋转或置换的量是偶数分量和行地址的预定函数，并且优选地通过根据s和n的最大值选择行地址的字段来获得，并且利用生成的掩码来屏蔽所选择的字段 从最小的s和n。
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公开(公告)号：US09391716B2
公开(公告)日：2016-07-12
申请号：US12753913
申请日：2010-04-05
IPC分类号： H04B10/80 , H04B10/114 , H04L12/64
CPC分类号： H04L47/70 , H04B10/1149 , H04B10/803 , H04L12/6402 , H04L41/12 , H04L47/50 , H04L49/25
摘要： A data center includes a plurality of computing units that communicate with each other using wireless communication, such as high frequency RF wireless communication. The data center may organize the computing units into groups (e.g., racks). In one implementation, each group may form a three-dimensional structure, such as a column having a free-space region for accommodating intra-group communication among computing units. The data center can include a number of features to facilitate communication, including dual-use memory for handling computing and buffering tasks, failsafe routing mechanisms, provisions to address permanent interface and hidden terminal scenarios, etc.
摘要翻译： 数据中心包括使用诸如高频RF无线通信之类的无线通信彼此通信的多个计算单元。 数据中心可以将计算单元组织成组（例如，机架）。 在一个实现中，每个组可以形成三维结构，诸如具有用于容纳计算单元之间的组内通信的自由空间区域的列。 数据中心可以包括一些便于通信的功能，包括用于处理计算和缓冲任务的双重使用内存，故障安全路由机制，解决永久接口和隐藏终端场景的规定等。
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公开(公告)号：US08156289B2
公开(公告)日：2012-04-10
申请号：US12131974
申请日：2008-06-03
申请人： David T. Harper, III
发明人： David T. Harper, III
IPC分类号： G06F12/00 , G06F15/167
CPC分类号： G06F9/3004 , G06F9/5088
摘要： The claimed matter provides systems and/or methods that effectuate utilization of fine-grained concurrency in parallel processing and efficient management of established memory structures. The system can include devices that establish memory structures associated with individual processors that can comprise a parallel processing phalanx. The system can thereafter utilize various enqueuing and/or dequeuing directives to add or remove work descriptors to or from the memory structures individually associated with each of the individual processors thereby providing improved work flow synchronization amongst the processors that comprise the parallel processing complex.
摘要翻译： 所要求保护的内容提供了在并行处理和有效管理已建立的存储器结构中实现细粒度并发性的系统和/或方法。 该系统可以包括建立与可以包括并行处理指骨的各个处理器相关联的存储器结构的设备。 该系统此后可以利用各种入队和/或出队指令来添加或删除与每个单独处理器单独关联的存储器结构的工作描述符，从而在包括并行处理复合体的处理器之间提供改进的工作流同步。
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公开(公告)号：US20090300333A1
公开(公告)日：2009-12-03
申请号：US12131974
申请日：2008-06-03
申请人： David T. Harper, III
发明人： David T. Harper, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/5088
摘要： The claimed matter provides systems and/or methods that effectuate utilization of fine-grained concurrency in parallel processing and efficient management of established memory structures. The system can include devices that establish memory structures associated with individual processors that can comprise a parallel processing phalanx. The system can thereafter utilize various enqueuing and/or dequeuing directives to add or remove work descriptors to or from the memory structures individually associated with each of the individual processors thereby providing improved work flow synchronization amongst the processors that comprise the parallel processing complex.
摘要翻译： 所要求保护的内容提供了在并行处理和有效管理已建立的存储器结构中实现细粒度并发性的系统和/或方法。 该系统可以包括建立与可以包括并行处理指骨的各个处理器相关联的存储器结构的设备。 该系统此后可以利用各种入队和/或出队指令来添加或删除与每个单独处理器单独关联的存储器结构的工作描述符，从而在包括并行处理复合体的处理器之间提供改进的工作流同步。
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