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1.发明授权公开(公告)号：US08949549B2
公开(公告)日：2015-02-03
申请号：US12324628
申请日：2008-11-26
CPC分类号： G06F9/526 , G06F3/067 , G06F12/0813
摘要： A method to exchange data in a shared memory system includes the use of a buffer in communication with a producer processor and a consumer processor. The cache data is temporarily stored in the buffer. The method includes for the consumer and the producer to indicate intent to acquire ownership of the buffer. In response to the indication of intent, the producer, consumer, buffer are prepared for the access. If the consumer intends to acquire the buffer, the producer places the cache data into the buffer. If the producer intends to acquire the buffer, the consumer removes the cache data from the buffer. The access to the buffer, however, is delayed until the producer, consumer, and the buffer are prepared.
摘要翻译： 在共享存储器系统中交换数据的方法包括使用与生产者处理器和消费者处理器进行通信的缓冲器。 高速缓存数据临时存储在缓冲区中。 该方法包括为消费者和生产者指示获取缓冲器所有权的意图。 响应于意图的指示，生产者，消费者，缓冲区准备进行访问。 如果消费者想要获取缓冲区，生产者将缓存数据放入缓冲区。 如果生产者打算获取缓冲区，消费者将从缓冲区中删除缓存数据。 然而，缓冲区的访问被延迟，直到生产者，消费者和缓冲区被准备好。
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2.发明申请公开(公告)号：US20100131720A1
公开(公告)日：2010-05-27
申请号：US12324628
申请日：2008-11-26
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F3/067 , G06F12/0813
摘要： A method to exchange data in a shared memory system includes the use of a buffer in communication with a producer processor and a consumer processor. The cache data is temporarily stored in the buffer. The method includes for the consumer and the producer to indicate intent to acquire ownership of the buffer. In response to the indication of intent, the producer, consumer, buffer are prepared for the access. If the consumer intends to acquire the buffer, the producer places the cache data into the buffer. If the producer intends to acquire the buffer, the consumer removes the cache data from the buffer. The access to the buffer, however, is delayed until the producer, consumer, and the buffer are prepared.
摘要翻译： 在共享存储器系统中交换数据的方法包括使用与生产者处理器和消费者处理器进行通信的缓冲器。 高速缓存数据临时存储在缓冲区中。 该方法包括为消费者和生产者指示获取缓冲器所有权的意图。 响应于意图的指示，生产者，消费者，缓冲区准备进行访问。 如果消费者想要获取缓冲区，生产者将缓存数据放入缓冲区。 如果生产者打算获取缓冲区，消费者将从缓冲区中删除缓存数据。 然而，缓冲区的访问被延迟，直到生产者，消费者和缓冲区被准备好。
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3.发明授权公开(公告)号：US08589867B2
公开(公告)日：2013-11-19
申请号：US12819108
申请日：2010-06-18
IPC分类号： G06F9/44
CPC分类号： G06F8/45
摘要： Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.
摘要翻译： 这里描述的是用于生成用于数据并行编程模型的调用存根的技术，使得以静态编译的高级编程语言编写的数据并行程序可以比传统方法更具声明性，可重复使用和便携式。 利用一些所描述的技术，调用存根由编译器生成，并且这些存根将数据并行计算的逻辑排列与用于该数据并行计算的目标数据并行硬件的实际物理排列相结合。
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公开(公告)号：US07426732B2
公开(公告)日：2008-09-16
申请号：US10683774
申请日：2003-10-10
申请人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Brian D. Koblenz , Richard D. Korry , Burton J. Smith
发明人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Brian D. Koblenz , Richard D. Korry , Burton J. Smith
IPC分类号： G06F9/46
CPC分类号： G06F9/485 , G06F9/461 , G06F9/4812 , G06F9/52 , G06F2209/481
摘要： A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.
摘要翻译： 一种方法和系统，准备一个从处理器利用率交换的任务，该处理器利用率在每台支持多个流的多个处理器的计算机上执行。 该任务具有一个或多个线程团队，每个团队都表示在单个处理器上执行的线程。 该任务为执行线程的每个流指定一个流作为团队主流，一个流作为任务主流。 对于每个团队主流，任务通知操作系统，当团队的每个其他线程已保存其状态并已退出其流时，该团队已准备好进行交换。 最后，对于任务主流，任务通知操作系统当任务准备好被交换时，它已经保存了状态，并且每个其他的团队已经通知它已经准备好被换出了。
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5.发明授权Method and system for identifying locations to move portions of the computer program 有权用于识别移动计算机程序部分的位置的方法和系统公开(公告)号：US06415433B1
公开(公告)日：2002-07-02
申请号：US09221031
申请日：1998-12-23
IPC分类号： G06F945
摘要： A method system for optimizing a computer program. In one embodiment, the system identifies depths of blocks of a computer program and identifies the availability of expressions of the computer program. The system then modifies the computer program when he identified availability of the expression and the identified depth of a block indicate that the expression can be moved to the block. The depth of the block may represent the number of dominator blocks of that block. The availability of the expression may represent the depth of a block to which the expression may be moved. In one embodiment, when the identified availability of the expression is less than the identified depth of the block, the expression can be moved to the block.
摘要翻译： 一种用于优化计算机程序的方法系统。 在一个实施例中，系统识别计算机程序的块的深度并且识别计算机程序的表达的可用性。 然后，系统在识别表达式的可用性时修改计算机程序，并且所识别的块的深度表示表达式可以移动到块。 块的深度可以表示该块的主导块的数量。 表达式的可用性可以表示可以移动表达式的块的深度。 在一个实施例中，当所识别的表达式的可用性小于所识别的块的深度时，表达式可以被移动到块。
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公开(公告)号：US06321379B1
公开(公告)日：2001-11-20
申请号：US09221287
申请日：1998-12-23
IPC分类号： G06F945
CPC分类号： G07F7/0866 , G06F8/445 , G06Q20/363
摘要： A computer-based method and system for allocating target registers to branch operations and for determining the location of target definitions for the branch operations within a computer program. The target register allocation system of the present invention allocates a target register to be specified by each branch operation. The target register is to contain the address of the target that is loaded by the target definition. The target register allocation system determines a location in the computer program for a target definition such that whenever the branch operation is executed, the allocated target register contains the address of the target of the branch. The target allocation system may determine the location to be in a dominator block of the branch operation. The target allocation system may also determine the location a target definition so that the address of the target that is loaded by the target definition can be used by multiple branch operations. The target allocation system may also determine the location of the target definition based on execution frequency of locations. The target allocation system may, when a branch operation is in a loop, determine the location of the target definition to be outside the loop. The target allocation system may, when the program is a function, give preference to a non-callee save register in allocating a target register. The target allocation system may give preference to a callee save register of a function whose invocation is located in between the determined location and the location of the branch operation on a path of execution when allocating a target register.
摘要翻译： 一种基于计算机的方法和系统，用于将目标寄存器分配到分支操作并用于确定计算机程序内的分支操作的目标定义的位置。 本发明的目标寄存器分配系统分配由每个分支操作指定的目标寄存器。 目标寄存器是包含由目标定义加载的目标地址。 目标寄存器分配系统确定用于目标定义的计算机程序中的位置，使得每当执行分支操作时，分配的目标寄存器包含分支目标的地址。 目标分配系统可以确定在分支操作的支配者块中的位置。 目标分配系统还可以确定目标定义的位置，使得由目标定义加载的目标的地址可以由多个分支操作使用。 目标分配系统还可以基于位置的执行频率来确定目标定义的位置。 当分支操作处于循环中时，目标分配系统可以确定目标定义在循环外的位置。 当程序是功能时，目标分配系统可以在分配目标寄存器时优先考虑非被调用者保存寄存器。 目标分配系统可以在分配目标寄存器时优先考虑其调用位于确定的位置和执行路径上的分支操作的位置之间的功能的被调用存储寄存器。
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公开(公告)号：US07165150B2
公开(公告)日：2007-01-16
申请号：US10697902
申请日：2003-10-30
申请人： Gail A. Alverson , Charles David Callahan, II , Simon H. Kahan , Brian D. Koblenz , Allan Porterfield , Burton J. Smith
发明人： Gail A. Alverson , Charles David Callahan, II , Simon H. Kahan , Brian D. Koblenz , Allan Porterfield , Burton J. Smith
IPC分类号： G06F12/08
CPC分类号： G06F9/52
摘要： Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.
摘要翻译： 使用存储器访问状态，指针和操作的访问控制字段以及多线程计算机系统中异常引发和异常捕获来处理数据的各种技术。 特别地，这些技术包括对一个字中被阻塞的线程的同步支持，对值的需求评估，多个线程到列表的并行访问，对数据缓冲器的同步和非同步访问，使用转发以避免检查 缓冲区，使用前哨字来检测通过数据结构的访问，使用不同的同步访问模式并发访问一个单词的内存，并使用陷阱来检测对受限内存的访问。
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公开(公告)号：US07117330B1
公开(公告)日：2006-10-03
申请号：US10461950
申请日：2003-06-12
申请人： Gail A. Alverson , Charles David Callahan, II , Simon H. Kahan , Brian D. Koblenz , Allan Porterfield , Burton J. Smith
发明人： Gail A. Alverson , Charles David Callahan, II , Simon H. Kahan , Brian D. Koblenz , Allan Porterfield , Burton J. Smith
IPC分类号： G06F12/00
CPC分类号： G06F9/52
摘要： Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.
摘要翻译： 使用存储器访问状态，指针和操作的访问控制字段以及多线程计算机系统中异常引发和异常捕获来处理数据的各种技术。 特别地，这些技术包括对一个字中被阻塞的线程的同步支持，对值的需求评估，多个线程到列表的并行访问，对数据缓冲器的同步和非同步访问，使用转发以避免检查 缓冲区，使用前哨字来检测通过数据结构的访问，使用不同的同步访问模式并发访问一个单词的内存，并使用陷阱来检测对受限内存的访问。
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公开(公告)号：US07020767B2
公开(公告)日：2006-03-28
申请号：US09792426
申请日：2001-02-23
申请人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Laurence S. Kaplan , Richard D. Korry
发明人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Laurence S. Kaplan , Richard D. Korry
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/542
摘要： A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a stream of the processor. During execution of the thread, the thread executes a loop that determines whether an event has occurred and, in response to determining whether an event has occurred, assigns a different thread to process the event so that multiple events can be processed in parallel and so that interrupts are not needed to signal that the event has occurred. Another aspect of the present invention provides a method and system for processing asynchronously occurring events without interrupt notifications. To achieve this processing, a first thread is executed to generate a notification that the event has occurred upon receipt of the asynchronously occurring event. A second thread is also executed that loops determining whether a notification has been generated and, in response to determining that a notification has been generated, performing the processing necessary for the event.
摘要翻译： 多线程处理器中的方法和系统，用于处理事件而无中断通知。 在本发明的一个方面，操作系统创建在处理器的流上执行的线程。 在执行线程期间，线程执行一个循环，该循环确定事件是否已经发生，并且响应于确定事件是否已经发生，分配不同的线程来处理事件，以便并行处理多个事件，从而 不需要中断来表明事件已经发生。 本发明的另一方面提供了一种用于处理异步发生的事件而不中断通知的方法和系统。 为了实现该处理，执行第一线程以生成在接收到异步发生的事件时已经发生事件的通知。 还执行第二线程，其循环确定是否已经生成通知，并且响应于确定已经生成通知，执行事件所需的处理。
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公开(公告)号：US06862635B1
公开(公告)日：2005-03-01
申请号：US09361671
申请日：1999-07-27
申请人： Gail A. Alverson , Charles David Callahan, II , Simon H. Kahan , Brian D. Koblenz , Allan Porterfield , Burton J. Smith
发明人： Gail A. Alverson , Charles David Callahan, II , Simon H. Kahan , Brian D. Koblenz , Allan Porterfield , Burton J. Smith
CPC分类号： G06F9/52
摘要： Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.
摘要翻译： 使用存储器访问状态，指针和操作的访问控制字段以及多线程计算机系统中异常引发和异常捕获来处理数据的各种技术。 特别地，这些技术包括对一个字中被阻塞的线程的同步支持，对值的需求评估，多个线程到列表的并行访问，对数据缓冲器的同步和非同步访问，使用转发以避免检查 缓冲区，使用前哨字来检测通过数据结构的访问，使用不同的同步访问模式并发访问一个单词的内存，并使用陷阱来检测对受限内存的访问。
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