TUNING VIA FACET WITH MINIMAL RIE LAG
    2.
    发明申请
    TUNING VIA FACET WITH MINIMAL RIE LAG 审中-公开
    通过最小的RIE LAG调整

    公开(公告)号:US20090068767A1

    公开(公告)日:2009-03-12

    申请号:US11854038

    申请日:2007-09-12

    IPC分类号: H01L21/00

    摘要: A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained.

    摘要翻译: 提供了一种设计蚀刻配方的方法。 执行蚀刻,包括提供具有设定的卤素与碳的比例的蚀刻气体,从蚀刻气体形成等离子体,以及蚀刻通过过孔的沟槽。 测量通过面。 卤素与碳的比例根据测量的通孔面重置,其中如果测量太多的小面积,则卤素与碳的比例将增加,并且如果测量的面积太小,则卤素与碳的比率降低。 重复前面的步骤,直到获得所需的刻面数量。