Method for reducing or eliminating de-lamination of semiconductor wafer film layers during a chemical mechanical planarization process
    3.
    发明授权
    Method for reducing or eliminating de-lamination of semiconductor wafer film layers during a chemical mechanical planarization process 失效
    在化学机械平面化处理中减少或消除半导体晶片薄膜层的去层压的方法

    公开(公告)号:US07040952B1

    公开(公告)日:2006-05-09

    申请号:US10186912

    申请日:2002-06-28

    IPC分类号: B24B49/00

    摘要: A method for preventing de-lamination of semiconductor wafer film stacks during a linear belt-type chemical mechanical planarization (CMP) process is provided. The method implements a pulsed polishing head rotation during a CMP process to maintain a slurry distribution across the width of a belt pad. The slurry distribution is maintained in a manner that prevents de-lamination of a wafer film having weak adhesion characteristics. Thus, the pulsed polishing head rotation implemented by the method reduces de-lamination of low-K material film layers during the CMP process.

    摘要翻译: 提供了一种用于在线性带式化学机械平面化(CMP)工艺期间防止半导体晶片膜堆叠的分层的方法。 该方法在CMP工艺期间实现脉冲抛光头旋转,以保持浆带分布跨过带垫的宽度。 浆料分布以防止具有弱粘附特性的晶片膜的去层压的方式保持。 因此,通过该方法实现的脉冲抛光头旋转在CMP工艺期间减少了低K材料膜层的去层压。

    Method and apparatus for detecting planarization of metal films prior to clearing
    4.
    发明授权
    Method and apparatus for detecting planarization of metal films prior to clearing 有权
    清除前检测金属膜平面化的方法和装置

    公开(公告)号:US07690966B1

    公开(公告)日:2010-04-06

    申请号:US12177067

    申请日:2008-07-21

    IPC分类号: B24B49/00

    CPC分类号: H01L21/7684 H01L22/20

    摘要: A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.

    摘要翻译: 提供了一种用于平面化半导体衬底的方法。 该方法通过跟踪对应于设置在半导体衬底上的导电膜的厚度的信号来启动。 然后,从表示跟踪信号的数据计算二阶导数。 接下来,基于二次导数的变化来识别平面化的开始。 还提供了被配置为识别CMP操作的阶段之间的转变的CMP系统。

    TUNING VIA FACET WITH MINIMAL RIE LAG
    5.
    发明申请
    TUNING VIA FACET WITH MINIMAL RIE LAG 审中-公开
    通过最小的RIE LAG调整

    公开(公告)号:US20090068767A1

    公开(公告)日:2009-03-12

    申请号:US11854038

    申请日:2007-09-12

    IPC分类号: H01L21/00

    摘要: A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained.

    摘要翻译: 提供了一种设计蚀刻配方的方法。 执行蚀刻,包括提供具有设定的卤素与碳的比例的蚀刻气体,从蚀刻气体形成等离子体,以及蚀刻通过过孔的沟槽。 测量通过面。 卤素与碳的比例根据测量的通孔面重置,其中如果测量太多的小面积,则卤素与碳的比例将增加,并且如果测量的面积太小,则卤素与碳的比率降低。 重复前面的步骤,直到获得所需的刻面数量。

    Interlocking chemical mechanical polishing system
    6.
    发明授权
    Interlocking chemical mechanical polishing system 失效
    联锁化学机械抛光系统

    公开(公告)号:US06475332B1

    公开(公告)日:2002-11-05

    申请号:US09684028

    申请日:2000-10-05

    IPC分类号: B24D1100

    CPC分类号: B24B37/26 B24B21/04 B24B47/00

    摘要: An interlocking polishing belt apparatus is disclosed. The interlocking polishing belt apparatus includes an interlocking belt, which includes a plurality of studs each having an upper stud end and a lower stud end. In addition, the interlocking polishing belt apparatus includes a polishing belt that is in contact with the interlocking belt. The polishing belt has a plurality of polishing belt stud holes, each configured to interlock with an upper stud end.

    摘要翻译: 公开了一种互锁的抛光带装置。 互锁抛光带装置包括互锁带,其包括多个螺柱,每个螺柱具有上螺柱端部和下螺柱端部。 此外,互锁抛光带装置包括与互锁带接触的研磨带。 抛光带具有多个抛光带螺栓孔,每个抛光带螺栓孔被构造成与上螺柱端部互锁。