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    Method of Constrained Aggressor Set Selection for Crosstalk Induced Noise
    1.
    发明申请
    Method of Constrained Aggressor Set Selection for Crosstalk Induced Noise 失效
    串扰导致噪声的约束进攻器集合选择方法

    公开(公告)号：US20090077515A1

    公开(公告)日：2009-03-19

    申请号：US11855323

    申请日：2007-09-14

    申请人： Debjit Sinha ,  Soroush Abbaspour ,  Ayesha Akhter ,  Gregory M. Schaeffer ,  David J. Widiger

    发明人： Debjit Sinha ,  Soroush Abbaspour ,  Ayesha Akhter ,  Gregory M. Schaeffer ,  David J. Widiger

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.

    摘要翻译： 执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响 。 给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。 类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。 此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。

    Method of constrained aggressor set selection for crosstalk induced noise
    2.
    发明授权
    Method of constrained aggressor set selection for crosstalk induced noise 失效
    串扰引起噪声的约束入侵者集合选择方法

    公开(公告)号：US07685549B2

    公开(公告)日：2010-03-23

    申请号：US11855323

    申请日：2007-09-14

    申请人： Debjit Sinha ,  Soroush Abbaspour ,  Ayesha Akhter ,  Gregory M. Schaeffer ,  David J. Widiger

    发明人： Debjit Sinha ,  Soroush Abbaspour ,  Ayesha Akhter ,  Gregory M. Schaeffer ,  David J. Widiger

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.

    摘要翻译： 执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响 。 给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。 类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。 此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。

    Method and apparatus for static timing analysis in the presence of a coupling event and process variation
    3.
    发明授权
    Method and apparatus for static timing analysis in the presence of a coupling event and process variation 失效
    在存在耦合事件和过程变化的情况下进行静态时序分析的方法和装置

    公开(公告)号：US07739640B2

    公开(公告)日：2010-06-15

    申请号：US11622979

    申请日：2007-01-12

    申请人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

    发明人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.

    摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。

    METHOD AND APPARATUS FOR STATIC TIMING ANALYSIS IN THE PRESENCE OF A COUPLING EVENT AND PROCESS VARIATION
    4.
    发明申请
    METHOD AND APPARATUS FOR STATIC TIMING ANALYSIS IN THE PRESENCE OF A COUPLING EVENT AND PROCESS VARIATION 失效
    联系事件和过程变化存在的静态时序分析方法与装置

    公开(公告)号：US20080172642A1

    公开(公告)日：2008-07-17

    申请号：US11622979

    申请日：2007-01-12

    申请人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

    发明人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.

    摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。

    Method for fast incremental calculation of an impact of coupled noise on timing
    5.
    发明授权
    Method for fast incremental calculation of an impact of coupled noise on timing 有权
    耦合噪声对定时影响的快速增量计算方法

    公开(公告)号：US07398491B2

    公开(公告)日：2008-07-08

    申请号：US11420529

    申请日：2006-05-26

    申请人： Gregory M. Schaeffer ,  Alexander J. Suess ,  David J. Hathaway

    发明人： Gregory M. Schaeffer ,  Alexander J. Suess ,  David J. Hathaway

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5036

    摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.

    摘要翻译： 一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。 然后执行对IC的一个或多个设计更改。 响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。 然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。

    METHOD FOR A FAST INCREMENTAL CALCULATION OF THE IMPACT OF COUPLED NOISE ON TIMING
    6.
    发明申请
    METHOD FOR A FAST INCREMENTAL CALCULATION OF THE IMPACT OF COUPLED NOISE ON TIMING 有权
    快速计算耦合噪声对时序影响的方法

    公开(公告)号：US20070277131A1

    公开(公告)日：2007-11-29

    申请号：US11420529

    申请日：2006-05-26

    申请人： Gregory M. Schaeffer ,  Alexander J. Suess ,  David J. Hathaway

    发明人： Gregory M. Schaeffer ,  Alexander J. Suess ,  David J. Hathaway

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5036

    摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.

    摘要翻译： 一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。 然后执行对IC的一个或多个设计更改。 响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。 然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。

    Prioritizing of nets for coupled noise analysis
    7.
    发明授权
    Prioritizing of nets for coupled noise analysis 失效
    耦合噪声分析网优先级

    公开(公告)号：US07181711B2

    公开(公告)日：2007-02-20

    申请号：US10908101

    申请日：2005-04-27

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  Gregory M. Schaeffer

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  Gregory M. Schaeffer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.

    摘要翻译： 一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。 优选地，随机噪声事件包括非时钟事件。 此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。 优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。

    Method to quickly estimate inductance for timing models
    9.
    发明授权
    Method to quickly estimate inductance for timing models 有权
    快速估计定时模型电感的方法

    公开(公告)号：US07750648B2

    公开(公告)日：2010-07-06

    申请号：US12059275

    申请日：2008-03-31

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  Mark R. Lasher ,  William J. Livingstone ,  Gregory M. Schaeffer

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  Mark R. Lasher ,  William J. Livingstone ,  Gregory M. Schaeffer

    IPC分类号： G01R27/00

    CPC分类号： G01R27/2611 ,  G01R27/28 ,  G06F17/5036 ,  G06F2217/84

    摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.

    摘要翻译： 估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。 此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。