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公开(公告)号：US20090257459A1
公开(公告)日：2009-10-15
申请号：US12492967
申请日：2009-06-26
申请人： Dennis C. FERGUSON , Devereaux C. CHEN , Eric M. VERWILLOW , Ramesh PADMANABHAN , Thomas Michael SKIBO
发明人： Dennis C. FERGUSON , Devereaux C. CHEN , Eric M. VERWILLOW , Ramesh PADMANABHAN , Thomas Michael SKIBO
IPC分类号： H04J3/06
CPC分类号： H04J3/1617 , H04J2203/0082 , H04L2007/045
摘要： A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET, The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets. sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.
摘要翻译： 发送系统在空闲时间间隔间时间填充期间，将输出数据流中的中断中止分组插入。 中断中止分组使得接收系统使其自身与发射系统同步，使得即使在帧间时间填充期间的错误导致接收系统进入错误状态，接收系统将在接收之前与发射系统同步 有效数据。 在一个实施例中，发送系统通过SONET发送分组中的数据，分组数据在发送端进行加扰并在接收端进行解扰。 Runt中止数据包。 在帧间时间间隔期间发送重新同步解扰器。 如果在帧间时间填充字节中存在错误，导致接收端解扰器不再与发送端加扰器同步，则中断中止分组将使解扰器与发送加扰器重新同步状态。
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公开(公告)号：US20110010474A1
公开(公告)日：2011-01-13
申请号：US12878810
申请日：2010-09-09
CPC分类号： G06F5/065 , G06F2207/3868
摘要： A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.
摘要翻译： 优化先进先出（FIFO）队列，以减少从FIFO中出现数据项的延迟。 在一个实现中，FIFO队列还包括连接到FIFO队列和旁路逻辑的输出的缓冲器。 缓冲器作为FIFO队列的最后阶段。 当缓冲区能够接收数据项且FIFO队列为空时，旁路逻辑会使输入数据项绕过FIFO并直接进入缓冲区。 在第二实施例中，仲裁逻辑被耦合到队列。 仲裁逻辑控制多路复用器从队列的多个最后阶段输出预定数量的数据项。 在该第二实施方式中，仲裁逻辑给队列的较后阶段的数据项赋予更高的优先级。
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公开(公告)号：US20110208926A1
公开(公告)日：2011-08-25
申请号：US13097921
申请日：2011-04-29
IPC分类号： G06F12/00
CPC分类号： G06F5/065 , G06F2207/3868
摘要： A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.
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