公开(公告)号：US07254656B2

公开(公告)日：2007-08-07

申请号：US10987657

申请日：2004-11-13

申请人： Derrin M. Berger ,  Jonathan Y. Chen ,  Thomas E. Gilbert

发明人： Derrin M. Berger ,  Jonathan Y. Chen ,  Thomas E. Gilbert

IPC分类号： G06F13/00

CPC分类号： G06F13/4027

摘要： A method and hardware design is disclosed for allowing the bring-up of a large scale system of interfaces that need to undergo a sequence of calibration steps. The method involves the use of a flexible broadcast scheme whereby groups of interfaces within a chip are assigned to groups to which commands can be broadcast. The scheme allows for the maximum amount of flexibility, allowing interfaces to be assigned to multiple groups which can overlap and be subsets of one another, and still allows for groups to be excluded from broadcast commands and be access individually. A method is also disclosed for using a chip-global status summary that can be accessed as any other register on the chip and can report calibration results for an entire chip with only one command. According to the invention a service utilizing the method embodied with code for implementing the method can now be provided.

摘要翻译： 公开了用于允许需要经历一系列校准步骤的大规模系统的接口的方法和硬件设计。 该方法涉及使用灵活广播方案，由此将芯片内的接口组分配给可以广播命令的组。 该方案允许最大的灵活性，允许将接口分配给可以重叠并且彼此子集的多个组，并且仍然允许将组排除在广播命令之外并且被单独访问。 还公开了一种用于使用芯片全局状态概要的方法，其可以作为芯片上的任何其他寄存器访问，并且可以仅用一个命令报告整个芯片的校准结果。 根据本发明，现在可以提供利用具有用于实现该方法的代码体现的方法的服务。

公开(公告)号：US07996715B2

公开(公告)日：2011-08-09

申请号：US12265137

申请日：2008-11-05

申请人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas E. Gilbert ,  Timothy G. McNamara ,  Patrick J. Meaney

发明人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas E. Gilbert ,  Timothy G. McNamara ,  Patrick J. Meaney

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/544 ,  G06F11/0709 ,  Y10S707/99931 ,  Y10S707/99939 ,  Y10S707/99943

摘要： A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

摘要翻译： 一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。 新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。 新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。

公开(公告)号：US20090070622A1

公开(公告)日：2009-03-12

申请号：US12265137

申请日：2008-11-05

申请人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas E. Gilbert ,  Timothy G. McNamara ,  Patrick J. Meaney

发明人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas E. Gilbert ,  Timothy G. McNamara ,  Patrick J. Meaney

IPC分类号： G06F11/20

CPC分类号： G06F11/0793 ,  G06F9/544 ,  G06F11/0709 ,  Y10S707/99931 ,  Y10S707/99939 ,  Y10S707/99943

摘要： A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

摘要翻译： 一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。 新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。 新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。

公开(公告)号：US07484118B2

公开(公告)日：2009-01-27

申请号：US11013728

申请日：2004-12-16

申请人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas E. Gilbert ,  Timothy G. McNamara ,  Patrick J. Meaney

发明人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas E. Gilbert ,  Timothy G. McNamara ,  Patrick J. Meaney

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/544 ,  G06F11/0709 ,  Y10S707/99931 ,  Y10S707/99939 ,  Y10S707/99943

摘要： The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

摘要翻译： 本发明提供了一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。 新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。 新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。