PHASE INTERPOLATOR CIRCUITRY FOR A BIT-LEVEL MODE RETIMER

    公开(公告)号:US20230122556A1

    公开(公告)日:2023-04-20

    申请号:US17935618

    申请日:2022-09-27

    IPC分类号: H04L7/033 H03H17/02 H04L7/00

    摘要: Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.

    Bit-level mode retimer
    2.
    发明授权

    公开(公告)号:US11489657B1

    公开(公告)日:2022-11-01

    申请号:US17451563

    申请日:2021-10-20

    IPC分类号: H04L7/033 H04L7/00 H03H17/02

    摘要: Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.