公开(公告)号：US5550990A

公开(公告)日：1996-08-27

申请号：US400425

申请日：1995-03-03

申请人： Don S. Keener ,  Andrew B. McNeill ,  Thomas H. Newsom ,  Kevin L. Scheiern ,  Richard W. Voorhees ,  Edward I. Wachtel

发明人： Don S. Keener ,  Andrew B. McNeill ,  Thomas H. Newsom ,  Kevin L. Scheiern ,  Richard W. Voorhees ,  Edward I. Wachtel

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4027

摘要： Arrangements for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

摘要翻译： 用于将具有良好定义的体系结构的总线物理划分为物理实体的布置，其中分区在逻辑上对于计算机和通过总线通信的设备是透明的，并且用于避免由于架构允许的动作的范围而潜在地产生的问题。 现有安排具有相关性的典型总线架构是与SCSI（小型计算机系统接口）总线相关联的。 允许在架构上发生的潜在问题涉及：（a）数据安全/完整性的暴露; （b）由于使用信号速率引起的过多的信号衰减，尽管架构允许这种信号速率对于架构也允许的特定总线负载环境是不合适的; （c）防止计算机与多个存储设备之间的数据并行传输的限制; （d）限制不适当地限制可连接到一条逻辑总线路径（计算机的一个输入 - 输出通道）的设备数量。 所公开的布置将总线划分成两个或更多个物理实体，其将计算机显示为一个逻辑实体。

公开(公告)号：US5293590A

公开(公告)日：1994-03-08

申请号：US864267

申请日：1992-04-06

申请人： Don S. Keener ,  Richard W. Voorhees

发明人： Don S. Keener ,  Richard W. Voorhees

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F13/10

CPC分类号： G06F13/385

摘要： This invention relates to personal computers and, more particularly, to a personal computer having an interface controller providing an economical way to achieve access to a direct access storage device by a small computer system interface. In accordance with this invention, the system CPU is selectively allowed to access all or only a portion of the internal registers in an interface controller, enabling implementation in conjunction with a conventional subsystem microprocessor interface to the registers if desired. With this change, either interface has full access to the interface controller's internal registers. By allowing such access, the number of component parts required can be reduced where multitasking possibilities are not desired, and the cost of providing SCSI capability significantly reduced.

摘要翻译： 本发明涉及个人计算机，更具体地，涉及一种具有接口控制器的个人计算机，该接口控制器提供经济的方式来实现通过小型计算机系统接口访问直接存取存储设备。 根据本发明，系统CPU被选择性地允许访问接口控制器中的全部或仅一部分内部寄存器，如果需要，使得能够结合常规子系统微处理器与寄存器的接口进行实现。 通过此更改，任一接口都可以完全访问接口控制器的内部寄存器。 通过允许这种访问，可以减少在不需要多任务可能性的情况下所需的组件数量，并且显着降低提供SCSI能力的成本。

公开(公告)号：US5550991A

公开(公告)日：1996-08-27

申请号：US411916

申请日：1995-03-28

申请人： Don S. Keener ,  Gregory J. Moore ,  Richard W. Voorhees

发明人： Don S. Keener ,  Gregory J. Moore ,  Richard W. Voorhees

IPC分类号： G06F13/38 ,  G06F13/28 ,  G06F13/00 ,  G06F12/00 ,  G06F13/10

CPC分类号： G06F13/28

摘要： This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory. The processor device and storage controller cooperate for exchange of blocks of data between the local processor bus and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus as necessary.

摘要翻译： 本发明涉及个人计算机，更具体地说，涉及使用直接耦合到本地处理器总线的小型计算机系统接口（SCSI）控制器的个人计算机，用于控制与诸如固定或可移动介质电磁存储设备之类的存储存储设备的数据传输。 个人计算机系统具有高速本地处理器数据总线，至少一个逻辑处理器设备直接耦合到本地处理器总线，并且能够通过本地处理器总线发送数据块传输的发生，并且存储控制器耦合 直接到本地处理器总线，用于调节处理器设备和存储存储设备之间的通信。 存储控制器具有用于暂时存储与本地处理器总线交换的数据块的FIFO存储器，并且能够通过本地处理器总线来发送FIFO存储器的状态。 当FIFO存储器具有待传输的数据之一和用于接收数据的空间以及通过本地处理器排空FIFO存储器时，处理器设备和存储控制器协作来交换本地处理器总线和FIFO存储器之间的数据块 巴士必要时。

公开(公告)号：US4979148A

公开(公告)日：1990-12-18

申请号：US281612

申请日：1988-12-09

申请人： Gregory F. Bush ,  Don S. Keener ,  Jeanne E. Morel ,  Richard W. Voorhees

发明人： Gregory F. Bush ,  Don S. Keener ,  Jeanne E. Morel ,  Richard W. Voorhees

IPC分类号： G06F12/06

CPC分类号： G06F12/0661

摘要： In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its outputs to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).