公开(公告)号：US20070099365A1

公开(公告)日：2007-05-03

申请号：US11586610

申请日：2006-10-26

申请人： Dong-Chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

发明人： Dong-Chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

IPC分类号： H01L21/8234

CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

公开(公告)号：US07518214B2

公开(公告)日：2009-04-14

申请号：US11586610

申请日：2006-10-26

申请人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

发明人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

IPC分类号： H01L29/00

CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。