摘要:
A masking addition operation apparatus for prevention of a side channel attack, includes a random value generation unit generating a first random value for a first input, second random value for a second input, and a summation random value. The masking addition operation apparatus includes an operation part performing an operation on the first and second random values, a previous carry input, and first and second masked random values generated based on the first and second random values. The masking addition operation apparatus includes a carry generator generating a carry input using a result of the operation part; and a summation bit generator generating a summation bit using the summation random value, the first and second random values, the previous carry input and the first and second masked random values.
摘要:
An apparatus for processing an F-function in a SEED encryption system includes: an arithmetic operation masking conversion unit for converting a logical operation mask value obtained by performing a logical operation of a SEED F-function input value and a random mask value into an arithmetic operation mask value; and a masking G-function unit for taking the arithmetic operation mask value from the arithmetic operation masking conversion unit as an input and producing an arithmetic operation output.
摘要:
A masking addition operation apparatus for prevention of a side channel attack, includes a random value generation unit generating a first random value for a first input, second random value for a second input, and a summation random value. The masking addition operation apparatus includes an operation part performing an operation on the first and second random values, a previous carry input, and first and second masked random values generated based on the first and second random values. The masking addition operation apparatus includes a carry generator generating a carry input using a result of the operation part; and a summation bit generator generating a summation bit using the summation random value, the first and second random values, the previous carry input and the first and second masked random values.
摘要:
An apparatus for processing an F-function in a SEED encryption system includes: an arithmetic operation masking conversion unit for converting a logical operation mask value obtained by performing a logical operation of a SEED F-function input value and a random mask value into an arithmetic operation mask value; and a masking G-function unit for taking the arithmetic operation mask value from the arithmetic operation masking conversion unit as an input and producing an arithmetic operation output.
摘要:
Disclosed is a method for implementing a symmetric key encryption algorithm against power analysis attacks, including: generating and storing an affine transform table; generating and storing a masked inversion table; and operating a masked S-box using the affine transform table and the masked inversion table.
摘要:
Disclosed is a method for implementing a symmetric key encryption algorithm against power analysis attacks, including: generating and storing an affine transform table; generating and storing a masked inversion table; and operating a masked S-box using the affine transform table and the masked inversion table.
摘要:
Provided are a secure device and method for preventing a side channel attack. The secure device includes a secure module converting plaintext data received from the outside into ciphertext data to thereby store the converted ciphertext data, or converting stored ciphertext data into plaintext data to thereby output the converted plaintext data, and a side channel attack sensing module sensing a side channel attack upon the secure module, and, according to the sensing result, allowing the secure module to stop operating, inducing malfunctions of the secure module, delaying operations of the secure module, or making the secure module a device having the secure module disabled. The secure device can safely protect an internal security algorithm and data from the side channel attack.
摘要:
An electronic tag for protecting privacy in RFID and a method of protecting privacy using the same are provided. Specifically, an RFID electronic tag capable of protecting privacy by authenticating an RFID reader and controlling access of the RFID reader to the RFID tag and a method of protecting privacy using the same are provided. The RFID electronic tag is applicable to a passive type RFID tag. The RFID electronic tag is also applicable to an ISO/IEC 18000-6 Type C tag that is a typical passive type RFID tag. It is possible to protect privacy of a user by controlling access of the RFID reader to the RFID tag and authenticating the RFID reader by modifying a tag inventory protocol and a memory map of the tag.
摘要:
A width and a length of the electrostatic discharge (ESD) protection circuit are reduced by changing a connection structure of the electrostatic discharge protection circuit. The ESD protection circuit includes a plurality of gate electrodes disposed between odd signal lines and even signal lines adjacent to the odd signal lines among the signal lines; source/drain electrode pairs each disposed on a respective one of the gate electrodes to form a plurality of transistors; and connection nodes parallel to the source/drain electrode pairs, each connection node adjacent to a respective one of the source/drain electrodes pairs and on a respective one of the gate electrodes, wherein each of the connection nodes is directly connected to the source/drain electrode pair of an adjacent transistor and the gate electrode formed below the source/drain electrode through a contact part.
摘要:
A width and a length of the electrostatic discharge (ESD) protection circuit are reduced by changing a connection structure of the electrostatic discharge protection circuit. The ESD protection circuit includes a plurality of gate electrodes disposed between odd signal lines and even signal lines adjacent to the odd signal lines among the signal lines; source/drain electrode pairs each disposed on a respective one of the gate electrodes to form a plurality of transistors; and connection nodes parallel to the source/drain electrode pairs, each connection node adjacent to a respective one of the source/drain electrodes pairs and on a respective one of the gate electrodes, wherein each of the connection nodes is directly connected to the source/drain electrode pair of an adjacent transistor and the gate electrode formed below the source/drain electrode through a contact part.