Test wafer and method for investigating electrostatic discharge induced wafer defects
    1.
    发明申请
    Test wafer and method for investigating electrostatic discharge induced wafer defects 失效
    测试晶片和调查静电放电诱发晶片缺陷的方法

    公开(公告)号:US20020076840A1

    公开(公告)日:2002-06-20

    申请号:US10071167

    申请日:2002-02-08

    发明人: Andreas Englisch

    IPC分类号: H01L021/66

    CPC分类号: H01L22/34 G03F1/40 G03F1/84

    摘要: A test wafer and method for investigating electrostatic discharge induced wafer defects are disclosed. The test wafer includes an electrostatic discharge (ESD) sensitive risk scale geometry, formed thereon. After exposure to a semiconductor manufacturing procedure, the test wafer may be analyzed by using the ESD risk scale geometry to identify and evaluate severity of any ESD effects associated with the semiconductor manufacturing procedure.

    摘要翻译: 公开了用于研究静电放电感应晶片缺陷的测试晶片和方法。 测试晶片包括在其上形成的静电放电(ESD)敏感的风险标度几何形状。 在暴露于半导体制造程序之后,可以通过使用ESD风险等级几何来分析测试晶片,以识别和评估与半导体制造过程相关的任何ESD效应的严重性。