摘要:
An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the semiconductor substrate, thereby providing a superior barrier to diffusion of moisture and contaminants from a window in the insulating layers to the semiconductor device regions.
摘要:
An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.
摘要:
An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.
摘要:
A physical implementation and method for achieving it are described for a load resistor and bus line subcircuit such as might be used in an SRAM cell. This was achieved by using two layers of polysilicon. The first polysilicon layer has low resistivity and serves to make effective contact to the drain regions of the FETs involved in the circuit. The second polysilicon layer has high resistivity and is used to form the load resistor as well as the collector bus line and resistor-drain connection. Formation of the latter two objects is achieved by providing a refractory metal underlay to the second polysilicon layer in the appropriate areas and then heating the structure so as to convert said refractory metal to its silicide. This process avoids the use of an ion implantation step during which some encroachment of the ions could occur, thereby retaining good control of the resistor dimensions.