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公开(公告)号:US20220037106A1
公开(公告)日:2022-02-03
申请号:US17377065
申请日:2021-07-15
Applicant: Elbit Systems of America, LLC
Inventor: Dan W. Chilcott , Arlynn W. Smith , John B. Hammond
Abstract: An apparatus, system and method is provided for producing stacked wafers containing an array of image intensifiers that can be evacuated on a wafer scale. The wafer scale fabrication techniques, including bonding, evacuation, and compression sealing concurrently forms a plurality of EBCMOS imager anodes with design elements that enable high voltage operation with optional enhancement of additional gain via TMSE amplification. The TMSE amplification is preferably one or more multiplication semiconductor wafers of an array of EBD die placed between a photocathode within a photocathode wafer and an imager anode that is preferably an EBCMOS imager anode bonded to or integrated within an interconnect die within an interconnect wafer.
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公开(公告)号:US11810747B2
公开(公告)日:2023-11-07
申请号:US17377065
申请日:2021-07-15
Applicant: Elbit Systems of America, LLC
Inventor: Dan W. Chilcott , Arlynn W. Smith , John B. Hammond
CPC classification number: H01J31/26 , H01J29/04 , H01J29/085
Abstract: An apparatus, system and method is provided for producing stacked wafers containing an array of image intensifiers that can be evacuated on a wafer scale. The wafer scale fabrication techniques, including bonding, evacuation, and compression sealing concurrently forms a plurality of EBCMOS imager anodes with design elements that enable high voltage operation with optional enhancement of additional gain via TMSE amplification. The TMSE amplification is preferably one or more multiplication semiconductor wafers of an array of EBD die placed between a photocathode within a photocathode wafer and an imager anode that is preferably an EBCMOS imager anode bonded to or integrated within an interconnect die within an interconnect wafer.
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公开(公告)号:US20210340007A1
公开(公告)日:2021-11-04
申请号:US17021630
申请日:2020-09-15
Applicant: ELBIT SYSTEMS OF AMERICA, LLC
Inventor: Dan W. Chilcott , Arlynn W. Smith
Abstract: The present disclosure relates to hermetic sealing of a device within a package or assembly. The sealable device is preferably a MEMS device. Surrounding the device is a first seal member that defines an internal cavity. The device can be positioned within the internal cavity, the extents of which defines a first seal region. A second seal member, and possibly others, is preferably positioned outside of the first seal member. The second seal member surrounds the first seal member a spaced distance from the first seal member to define a second seal region. Getter material is preferably placed within the first and second seal regions, and the first and second seal regions are sealed under vacuum pressure to provide a MEMS packaged assembly having a relatively low leak rate.
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