公开(公告)号：US20220223213A1

公开(公告)日：2022-07-14

申请号：US17149689

申请日：2021-01-14

Applicant: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.

Inventor： MING-XUN WANG ,  CHIH-HAO CHEN ,  JI-JR LUO

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/30 ,  G11C16/26 ,  G11C16/24

Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.