公开(公告)号：US11699423B1

公开(公告)日：2023-07-11

申请号：US17583235

申请日：2022-01-25

Applicant: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.

Inventor： Hsin-Yuan Chiu ,  Hsiang-Yu Yang ,  Ya-Mien Hsu

IPC: G10K11/178 ,  H03G3/00

CPC classification number: G10K11/17813 ,  H03G3/001

Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.

公开(公告)号：US20220400341A1

公开(公告)日：2022-12-15

申请号：US17344907

申请日：2021-06-10

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Hsin-Yuan Chiu ,  Tsung-Fu Lin

IPC: H04R3/04 ,  H03G5/16 ,  H03G5/02 ,  H03G5/00

Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

公开(公告)号：US11368130B1

公开(公告)日：2022-06-21

申请号：US17179375

申请日：2021-02-18

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Hsin-Yuan Chiu ,  Hsiang-Yu Yang

IPC: H03F3/217 ,  H03F1/52 ,  H03F3/38

Abstract: A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

公开(公告)号：US11601753B2

公开(公告)日：2023-03-07

申请号：US17344907

申请日：2021-06-10

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Hsin-Yuan Chiu ,  Tsung-Fu Lin

IPC: H04R3/14 ,  H03G5/00 ,  H04R3/04 ,  H03G5/02 ,  H03G5/16

Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

公开(公告)号：US11489499B1

公开(公告)日：2022-11-01

申请号：US17396853

申请日：2021-08-09

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Tsung-Fu Lin ,  Hsin-Yuan Chiu

IPC: H03F3/217 ,  H03F3/38 ,  H03F1/02

Abstract: A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.