公开(公告)号：US11327664B1

公开(公告)日：2022-05-10

申请号：US15668797

申请日：2017-08-04

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Jaeyoo Jung ,  Ramesh Doddaiah ,  Venkata Khambam ,  Earl Medeiros ,  Richard Trabing

IPC: G06F3/06

Abstract: A portion of the shared global memory of a storage array is allocated for write-only blocks. Writes to a same-block of a production device may be accumulated in the allocated portion of memory. Temporal sequencing may be associated with each accumulated version of the same-block. When idle processing resources become available, the oldest group of same-blocks may be consolidated based on the temporal sequencing. The consolidated block may then be destaged to cache slots or managed drives. A group of same-blocks may also be consolidated in response to a read command.

公开(公告)号：US11016896B2

公开(公告)日：2021-05-25

申请号：US16750067

申请日：2020-01-23

Applicant: EMC IP Holding Company LLC

Inventor： Venkata Khambam ,  Jeffrey R. Nelson ,  Brian Asselin ,  Rong Yu

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0815

Abstract: Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different ones of the processors may be placed on different directors.

公开(公告)号：US20190332528A1

公开(公告)日：2019-10-31

申请号：US15964315

申请日：2018-04-27

Applicant: EMC IP Holding Company LLC

Inventor： Venkata Khambam ,  Jeffrey R. Nelson ,  Brian Asselin ,  Rong Yu

IPC: G06F12/084 ,  G06F12/0815 ,  G06F12/0842

Abstract: Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different ones of the processors may be placed on different directors.

公开(公告)号：US10579529B2

公开(公告)日：2020-03-03

申请号：US15964315

申请日：2018-04-27

Applicant: EMC IP Holding Company LLC

Inventor： Venkata Khambam ,  Jeffrey R. Nelson ,  Brian Asselin ,  Rong Yu

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0815

Abstract: Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different ones of the processors may be placed on different directors.