公开(公告)号：US10949359B2

公开(公告)日：2021-03-16

申请号：US15961402

申请日：2018-04-24

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Kaustubh S. Sahasrabudhe ,  Mark D. Moreau ,  Malak Alshawabkeh ,  Earl Medeiros

IPC: G06F12/122 ,  G06F12/0815

Abstract: Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.

公开(公告)号：US20190324921A1

公开(公告)日：2019-10-24

申请号：US15961402

申请日：2018-04-24

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Kaustubh S. Sahasrabudhe ,  Mark D. Moreau ,  Malak Alshawabkeh ,  Earl Medeiros

IPC: G06F12/122 ,  G06F12/0815

Abstract: Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.

公开(公告)号：US11537313B1

公开(公告)日：2022-12-27

申请号：US17399129

申请日：2021-08-11

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Jason J Duquette ,  James M Guyer ,  Thomas Mackintosh ,  Earl Medeiros

IPC: G06F3/06

Abstract: Mirrored volatile memory in a storage system is configured with a dual cast region of addresses. Buffers in the dual cast region are allocated for data associated with a received Write IO. A host IO device associates the dual cast addresses with the data. A switch or CPU complex recognizes the dual cast addresses associated with the data and, in response, creates and sends a first copy of the data to a first volatile memory mirror and creates and sends a second copy of the data to a second volatile memory mirror. The second copy may be sent via PCIe NTB between switches or CPU complexes.

公开(公告)号：US20220237112A1

公开(公告)日：2022-07-28

申请号：US17159327

申请日：2021-01-27

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Michael Scharland ,  Earl Medeiros ,  Parmeshwr Prasad

IPC: G06F12/02 ,  G06F12/1045 ,  G06F12/0873 ,  G06F3/06

Abstract: The present disclosure relates to one or more memory management techniques. In embodiments, one or more regions of storage class memory (SCM) of a storage array is provisioned as expanded global memory. The one or more regions can correspond to SCM persistent cache memory regions. The storage array's global memory and expanded global memory can be used to execute one or more storage-related services connected to servicing (e.g., executing) an input/output (IO) operation.

公开(公告)号：US20220100412A1

公开(公告)日：2022-03-31

申请号：US17034032

申请日：2020-09-28

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Earl Medeiros ,  Parmeshwr Prasad ,  Rahul Deo Vishwakarma

IPC: G06F3/06

Abstract: Non-volatile Random Access Memory (NVR) on a storage system may be dynamically converted between use as temporary memory in a memory context and use as persistent memory in a storage context. NVR (e.g., embodied as DIMM) may be utilized in a hybrid capacity, where some of the NVR is used as memory and some of the NVR is used as storage, and where NVR memory is converted to memory as needed, dynamically as I/O is being processed using the NVR. A host system may be directly connected to an internal switching fabric of the data storage system without an intervening component of the storage system (e.g., a director) controlling access of the host system to the internal fabric or to the memory. The host system may provision and use the NVR as storage by directly communicating with the NVR over the internal fabric, for example, using RDMA.

公开(公告)号：US11782634B2

公开(公告)日：2023-10-10

申请号：US17034032

申请日：2020-09-28

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Earl Medeiros ,  Parmeshwr Prasad ,  Rahul Deo Vishwakarma

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0679

Abstract: Non-volatile Random Access Memory (NVR) on a storage system may be dynamically converted between use as temporary memory in a memory context and use as persistent memory in a storage context. NVR (e.g., embodied as DIMM) may be utilized in a hybrid capacity, where some of the NVR is used as memory and some of the NVR is used as storage, and where NVR memory is converted to memory as needed, dynamically as I/O is being processed using the NVR. A host system may be directly connected to an internal switching fabric of the data storage system without an intervening component of the storage system (e.g., a director) controlling access of the host system to the internal fabric or to the memory. The host system may provision and use the NVR as storage by directly communicating with the NVR over the internal fabric, for example, using RDMA.

公开(公告)号：US11687443B2

公开(公告)日：2023-06-27

申请号：US17159327

申请日：2021-01-27

Applicant: EMC IP Holding Company LLC

Inventor： Owen Martin ,  Michael Scharland ,  Earl Medeiros ,  Parmeshwr Prasad

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0873 ,  G06F12/1045

CPC classification number: G06F12/0238 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0873 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/7201

Abstract: The present disclosure relates to one or more memory management techniques. In embodiments, one or more regions of storage class memory (SCM) of a storage array is provisioned as expanded global memory. The one or more regions can correspond to SCM persistent cache memory regions. The storage array's global memory and expanded global memory can be used to execute one or more storage-related services connected to servicing (e.g., executing) an input/output (IO) operation.

公开(公告)号：US11327664B1

公开(公告)日：2022-05-10

申请号：US15668797

申请日：2017-08-04

Applicant: EMC IP HOLDING COMPANY LLC

Inventor： Jaeyoo Jung ,  Ramesh Doddaiah ,  Venkata Khambam ,  Earl Medeiros ,  Richard Trabing

IPC: G06F3/06

Abstract: A portion of the shared global memory of a storage array is allocated for write-only blocks. Writes to a same-block of a production device may be accumulated in the allocated portion of memory. Temporal sequencing may be associated with each accumulated version of the same-block. When idle processing resources become available, the oldest group of same-blocks may be consolidated based on the temporal sequencing. The consolidated block may then be destaged to cache slots or managed drives. A group of same-blocks may also be consolidated in response to a read command.