公开(公告)号：US12224757B2

公开(公告)日：2025-02-11

申请号：US18117795

申请日：2023-03-06

Applicant: ESS Technology, Inc.

Inventor： Dustin Dale Forman ,  Libin Timothy George ,  Hassan Mohammadnavazi ,  Hu Jing Yao

IPC: H03L7/091 ,  H03L7/089 ,  H03L7/099

Abstract: A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.

公开(公告)号：US20240305304A1

公开(公告)日：2024-09-12

申请号：US18117795

申请日：2023-03-06

Applicant: ESS Technology, Inc.

Inventor： Dustin Dale Forman ,  Libin Timothy George ,  Hassan Mohammadnavazi ,  Hu Jing Yao

IPC: H03L7/091 ,  H03L7/089 ,  H03L7/099

CPC classification number: H03L7/091 ,  H03L7/0891 ,  H03L7/099

Abstract: A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.