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    High data density RISC processor
    6.
    发明授权
    High data density RISC processor 有权
    高数据密度RISC处理器

    公开(公告)号：US06282633B1

    公开(公告)日：2001-08-28

    申请号：US09192395

    申请日：1998-11-13

    申请人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson

    发明人： Earl A. Killian ,  Ricardo E. Gonzalez ,  Ashish B. Dixit ,  Monica Lam ,  Walter D. Lichtenstein ,  Christopher Rowen ,  John C. Ruttenberg ,  Robert P. Wilson

    IPC分类号： G06K930

    CPC分类号： G06F9/30178 ,  G06F9/30145 ,  G06F9/30167

    摘要： A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.

    摘要翻译： RISC处理器实现指令集，除了优化执行程序所需的指令数，时钟周期和每个指令的平均时钟数之间的关系外，还设计用于优化方程S = IS * BI， 其中S是以位为单位的程序指令的大小，IS是表示程序所需的指令的静态数量（而不是执行所需的数目），BI是每个指令的平均位数。 与传统的RISC体系结构相比，该处理器降低了BI和IS，时钟周期和每个指令的平均时钟周期几乎没有增加。 处理器在基于RISC原理的固定长度高性能编码中提供了良好的代码密度，包括具有加载/存储架构的通用寄存器。 此外，处理器实现了保持高性能的简单可变长度编码。