公开(公告)号：US07372326B1

公开(公告)日：2008-05-13

申请号：US11549011

申请日：2006-10-12

申请人： Edward T. Spears ,  Douglas A. Teeter ,  Hien D. Bui

发明人： Edward T. Spears ,  Douglas A. Teeter ,  Hien D. Bui

IPC分类号： H03F1/14

CPC分类号： H03F1/0277

摘要： The present invention is a parallel RF amplifier circuit that selects between a high power side (HPS) and a low power side (LPS), depending upon output power. A chain matching network couples an LPS output to an HPS output for improved efficiency at lower output power. When the HPS is selected, the LPS output is disabled, and when the LPS is selected, the HPS output is disabled When the HPS is selected, large signal voltage swings from the collector of the HPS amplifier may be multiplied through the chain matching network, and may cause negative voltage swings at the LPS collector, which may degrade linearity and efficiency of the HPS amplifier by driving currents into the disabled LPS amplifier. Therefore, the present invention includes LPS bias circuitry to minimize impacts of negative voltage swings at the LPS output.

摘要翻译： 本发明是根据输出功率在大功率侧（HPS）和低功率侧（LPS）之间进行选择的并行RF放大电路。 链匹配网络将LPS输出耦合到HPS输出，以在更低的输出功率下提高效率。 当选择HPS时，LPS输出被禁止，当选择LPS时，HPS输出被禁用当选择HPS时，来自HPS放大器的集电极的大的信号电压摆幅可以通过链匹配网络相乘， 并且可能在LPS集电极处引起负电压摆幅，这可能通过驱动电流进入禁用的LPS放大器来降低HPS放大器的线性度和效率。 因此，本发明包括LPS偏压电路，以最小化LPS输出处的负电压摆幅的影响。

公开(公告)号：US06266629B1

公开(公告)日：2001-07-24

申请号：US09182378

申请日：1998-10-29

申请人： Raghuveer Mallavarpu ,  Douglas A. Teeter

发明人： Raghuveer Mallavarpu ,  Douglas A. Teeter

IPC分类号： G06G762

CPC分类号： G06F17/5036

摘要： A method is provided for large signal modeling of a field effect transistor. The method includes establishing a small signal model for the transistor, such model having a gate-source capacitance Cgs and a drain-gate capacitance Cdg, both being functions of a gate-source voltage Vgs and a drain-source voltage Vds. The s-parameters of the transistor are measured and curve fitting is applied to the measured s-parameters to establish small signal model parameters. The small signal model parameters include gate-source capacitance Cgs as a function of Vgs and Vds and gate-drain capacitance Cdg as a function of Vgs and Vds. Curve fitting is applied to Cgs and Cdg to establish large signal gate charge fitting parameters. The established large signal gate charge fitting parameters are used to express a gate-source charge Qgs and a gate-drain charge Qgd as functions of Vgs and a gate-drain voltage Vgd in a large signal model for the transistor.

摘要翻译： 提供了一种用于场效应晶体管的大信号建模的方法。 该方法包括为晶体管建立一个小信号模型，这种模型具有栅极 - 源极电容Cgs和漏极 - 栅极电容Cdg，它们都是栅极 - 源极电压Vgs和漏极 - 源极电压Vds的函数。 测量晶体管的s参数，并将曲线拟合应用于测量的s参数以建立小信号模型参数。 小信号模型参数包括作为Vgs和Vds的函数的栅源电容Cgs和作为Vgs和Vds的函数的栅极 - 漏极电容Cdg。 曲线拟合应用于Cgs和Cdg以建立大信号门电荷拟合参数。 所建立的大信号栅极电荷拟合参数用于在晶体管的大信号模型中表示栅源电荷Qgs和栅极 - 漏极电荷Qgd作为Vgs的函数和栅极 - 漏极电压Vgd。

公开(公告)号：US06232840B1

公开(公告)日：2001-05-15

申请号：US09329676

申请日：1999-06-10

申请人： Douglas A. Teeter ,  Aryeh Platzker

发明人： Douglas A. Teeter ,  Aryeh Platzker

IPC分类号： H03F368

CPC分类号： H03F1/083 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/366 ,  H03F2200/75

摘要： A transistor device having a plurality of transistor cells. Each one of the cells has a control electrode for controlling a flow of carriers through a semiconductor. The device has an input node. A plurality of filters is provided. Each one of the filters is coupled between the input node and a corresponding one of the control electrodes of the plurality of transistor cells. In one embodiment of the invention, pairs of the control electrodes are connected to a common region and wherein each one of the filters is coupled between the input node and a corresponding one of the common regions. The semiconductor provides a common active region for the plurality of transistor cells. Each one of the filters comprises: a conductive layer; a dielectric layer disposed on the conductive layer; a resistive layer disposed over the dielectric layer; a conductive electrode disposed in electrical contact with a first portion of the resistive layer and providing the input node; and, a connector in electrical contact with a second portion of the resistive layer such second portion of the resistive layer being displaced from the first portion of the resistive layer, such connector passing through the dielectric and being in electrical contact with the first conductor.

摘要翻译： 一种具有多个晶体管单元的晶体管器件。 每个单元具有用于控制通过半导体的载流子流动的控制电极。 该设备有一个输入节点。 提供多个滤波器。 滤波器中的每一个耦合在输入节点和多个晶体管单元中的对应的一个控制电极之间。 在本发明的一个实施例中，成对的控制电极连接到公共区域，并且其中每个滤波器耦合在输入节点和相应的公共区域之间。 半导体为多个晶体管单元提供公共有源区。 每个滤波器包括：导电层; 布置在所述导电层上的电介质层; 设置在电介质层上的电阻层; 导电电极，设置成与所述电阻层的第一部分电接触并提供所述输入节点; 以及与所述电阻层的第二部分电接触的连接器，所述电阻层的所述第二部分从所述电阻层的所述第一部分移位，所述连接器穿过所述电介质并与所述第一导体电接触。