公开(公告)号：US20070262976A1

公开(公告)日：2007-11-15

申请号：US11665207

申请日：2005-09-16

Applicant: Eiji Matsuda ,  Makoto Yokoyama ,  Yuhichirou Murakami

Inventor： Eiji Matsuda ,  Makoto Yokoyama ,  Yuhichirou Murakami

IPC: G09G5/00 ,  H03L5/00

CPC classification number: G09G3/3688 ,  G09G3/3611 ,  G09G2310/0283 ,  G09G2310/0289 ,  H03K3/356104 ,  H03K19/0016

Abstract: In one embodiment, in accordance with a timing at which each of output signals of a source shift register is inputted, a level shifter control circuit generates a control signal for controlling a level shift operation of a level shifter. An input interval between the output signals of the source shift register is shorter than an active period of a clock signal. In case of stopping the level shift operation, the level shifter keeps an output signal at a state before stoppage of the level shift operation. As a result, it is possible to reduce power consumption of the level shifter circuit.

Abstract translation: 在一个实施例中，根据输入源移位寄存器的每个输出信号的定时，电平移位器控制电路产生用于控制电平移位器的电平移位操作的控制信号。 源极移位寄存器的输出信号之间的输入间隔比时钟信号的有效周期短。 在停止电平移位操作的情况下，电平移位器将输出信号保持在停止电平移位操作之前的状态。 结果，可以降低电平移位器电路的功耗。