公开(公告)号：US09293099B2

公开(公告)日：2016-03-22

申请号：US14124020

申请日：2012-06-25

Applicant: Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Seijirou Gyouten

Inventor： Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Seijirou Gyouten

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3648 ,  G09G3/3655 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

Abstract: A retention circuit (22) corresponding to each stage of a shift register is configured such that, when SROUT(k−1) is active, an input terminal of an inverter (INV1) and an output terminal of an inverter (INV2) are electrically connected to each other and an output terminal of the inverter (INV1) and an input terminal of the inverter (INV2) are connected to each other. This makes it possible to reduce a circuit scale of a display driving circuit without causing any malfunction of the display driving circuit.

Abstract translation: 对应于移位寄存器的各级的保持电路（22）被配置成当SROUT（k-1）有效时，逆变器（INV1）的输入端子和反相器（INV2）的输出端子是电气 连接到逆变器（INV1）的输出端子和逆变器（INV2）的输入端子彼此连接。 这使得可以减少显示驱动电路的电路规模而不会引起显示驱动电路的任何故障。

公开(公告)号：US09124260B2

公开(公告)日：2015-09-01

申请号：US14124018

申请日：2012-06-25

Applicant: Shige Furuta ,  Yuhichiroh Murakami ,  Makoto Yokoyama ,  Seijirou Gyouten

Inventor： Shige Furuta ,  Yuhichiroh Murakami ,  Makoto Yokoyama ,  Seijirou Gyouten

IPC: G09G3/36 ,  H03K3/356

CPC classification number: H03K3/356104 ,  G09G3/3648

Abstract: A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.

Abstract translation: 触发器电路（11a）包括：具有连接到SB端子的栅极端子的输入晶体管（Tr19），连接到RB端子的源极端子和连接到第一CMOS电路的漏极端子 第二CMOS电路; 连接到第一CMOS电路或第二CMOS电路的电源（VSS），当SB信号变为有效时，连接到RB端子; 和稳压电路（RC）。 通过这种布置，提供了一种紧凑型触发器和采用触发器的紧凑型移位寄存器，而不会引起触发器和移位寄存器的故障。

公开(公告)号：US09070471B2

公开(公告)日：2015-06-30

申请号：US13377838

申请日：2010-03-18

Applicant: Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki ,  Yuhichiroh Murakami

Inventor： Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki ,  Yuhichiroh Murakami

IPC: G09G3/36 ,  G06F3/038 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/063

Abstract: Provided is a shift register of a display-driving circuit which carries out simultaneous selection of a plurality of signal lines by using a simultaneous selection signal. A stage of the shift register includes (i) a set-reset type flip-flop and (ii) a signal generating circuit which generates an output signal of the stage by selectively outputting a signal in response to an output of the flip-flop. The output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active while the simultaneous selection is being performed, and the output from the flip-flop is inactive during a period in which a setting signal and a resetting signal are both being active. This makes it possible to quickly carry out the simultaneous selection of all the signal lines and the initialization of the shift register.

Abstract translation: 提供了一种显示驱动电路的移位寄存器，其通过使用同时选择信号来执行多个信号线的同时选择。 移位寄存器的一级包括（i）设置复位型触发器和（ii）信号发生电路，其通过响应于触发器的输出选择性地输出信号来产生该级的输出信号。 由于同时选择信号的激活，阶段（i）的输出信号变为有效，然后（ii）在执行同时选择时保持有效，并且触发器的输出在其中 设定信号和复位信号均处于活动状态。 这使得可以快速地执行所有信号线的同时选择和移位寄存器的初始化。

公开(公告)号：US20130257846A1

公开(公告)日：2013-10-03

申请号：US13993922

申请日：2011-12-12

Applicant: Eiji Matsuda ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Seijirou Gyouten ,  Shuji Nishi ,  Makoto Yokoyama

Inventor： Eiji Matsuda ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Seijirou Gyouten ,  Shuji Nishi ,  Makoto Yokoyama

IPC: G09G3/36

CPC classification number: G09G3/3618 ,  G09G3/3648 ,  G09G2300/0852 ,  G09G2300/0857 ,  G09G2300/0876

Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Abstract translation: 记忆型液晶显示装置包括晶体管（N1，N2），保持电极（MRY），刷新输出控制部分（RS1）和电容器（Cb1）。 在数据保持期间，通过改变提供给相应的CS行的保持电容配线信号的电位电平，经由相应的一个电容器（Cb1）来改变每个保持电极（MRY）的电位 （CSL（i））。 每个刷新输出控制部分（RS1）经由输入部分接收相应的一个保持电极（MRY）所改变的电位，并根据电位控制对应的像素电极（PIX）的电位 从而改变了。

公开(公告)号：US20120105395A1

公开(公告)日：2012-05-03

申请号：US13378233

申请日：2010-03-18

Applicant: Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

Inventor： Takuya Hachida ,  Yuhichiroh Murakami ,  Shige Furuta ,  Makoto Yokoyama ,  Yasushi Sasaki

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/063

Abstract: A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.

Abstract translation: 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。

公开(公告)号：US20120092323A1

公开(公告)日：2012-04-19

申请号：US13378214

申请日：2010-03-26

Applicant: Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Makoto Yokoyama ,  Takahiro Yamaguchi

Inventor： Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Makoto Yokoyama ,  Takahiro Yamaguchi

IPC: G09G5/00 ,  H03K3/356

CPC classification number: G09G3/3677 ,  G09G3/3655 ,  G09G3/3688 ,  G09G2300/0876 ,  G09G2310/0286 ,  G11C19/28 ,  H03K3/356104

Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

Abstract translation: 触发器包括：第一，第二，第三和第四晶体管; 输入端子; 以及第一和第二输出端子，构成第一CMOS电路的第一和第二晶体管使得栅极端子连接并且漏极端子连接，第三和第四晶体管构成第二CMOS电路，使得栅极端子连接并且漏极端子被连接 连接到第一CMOS电路的栅极侧的第一输出端子和第二CMOS电路的漏极侧，第二输出端子连接到第二CMOS电路的栅极侧和第一CMOS电路的漏极侧， 包括在第一至第四晶体管组中的至少一个输入晶体管，输入晶体管的源极端子连接到输入端子之一。 这可以提供更紧凑的触发器。

公开(公告)号：US07220762B1

公开(公告)日：2007-05-22

申请号：US10110679

申请日：2000-10-19

Applicant: Koji Ukai ,  Satoshi Fujioka ,  Mitsuru Mizuno ,  Makoto Yokoyama ,  Shigeru Aoki ,  Masao Kawamura

Inventor： Koji Ukai ,  Satoshi Fujioka ,  Mitsuru Mizuno ,  Makoto Yokoyama ,  Shigeru Aoki ,  Masao Kawamura

IPC: A61K31/4184 ,  A61K31/4439 ,  C07D401/12

CPC classification number: A61K9/2886 ,  A61K9/2009 ,  A61K9/2027 ,  A61K31/4439 ,  A61K47/02 ,  A61K47/32 ,  C07D401/12

Abstract: The present invention provides a method for stabilizing an oral solid formulation containing a benzimidazole-based compound or a physiologically acceptable salt thereof. That is, it provides a method for stabilizing a benzimidazole-based compound or a physiologically acceptable salt thereof, comprising incorporating 1) a crospovidone or a crospovidone and 2) sodium hydroxide and/or potassium hydroxide to a benzimidazole-based compound or a physiologically acceptable salt thereof.

Abstract translation: 本发明提供一种稳定含有苯并咪唑类化合物或其生理上可接受的盐的口服固体制剂的方法。 也就是说，它提供了一种稳定基于苯并咪唑的化合物或其生理上可接受的盐的方法，包括将1）交聚维酮或交联聚维酮和2）氢氧化钠和/或氢氧化钾加入苯并咪唑基化合物或生理上可接受的盐 的盐。

公开(公告)号：US06755734B2

公开(公告)日：2004-06-29

申请号：US10267449

申请日：2002-10-08

Applicant: Makoto Yokoyama ,  Keiichi Ono ,  Fumiyuki Tamura

Inventor： Makoto Yokoyama ,  Keiichi Ono ,  Fumiyuki Tamura

IPC: B01L104

CPC classification number: F24F3/161 ,  F24F11/39 ,  F24F11/77 ,  F24F11/79 ,  H01L21/67017 ,  H01L21/67253

Abstract: Information from fan filter units and differential pressure gauges provided in a ceiling of a clean room is used to control directions and volumes of air flows blown from respective fan filter units. In order to improve a wind velocity distribution in the clean room, pressure in a ceiling chamber is made uniform and control of the FFU revolution speeds of fan filter units is made easy. In order to control directions of air flows in the clean room, damper adjusting mechanisms are provided under a grating floor of the clean room. Such arrangement enables optimizing an operating condition of the clean room and achieving energy saving.

Abstract translation: 用于设置在洁净室的天花板上的风扇过滤器单元和差压计的信息用于控制从各个风扇过滤器单元吹送的空气流的方向和体积。 为了提高洁净室内的风速分布，使天花板室内的压力均匀，并且容易控制风扇过滤器单元的FFU转速。 为了控制洁净室中的空气流动方向，在洁净室的格栅地板下设置阻尼器调节机构。 这样的布置使得能够优化洁净室的运行状态并实现节能。

公开(公告)号：US6156090A

公开(公告)日：2000-12-05

申请号：US164582

申请日：1998-10-01

Applicant: Tominori Ishikawa ,  Yuji Toyama ,  Makoto Yokoyama ,  Yoshihiro Takada ,  Keiichi Honma ,  Osamu Kawasaki ,  Masayosi Inoue ,  Kazunari Sugai ,  Jun Tazawa

Inventor： Tominori Ishikawa ,  Yuji Toyama ,  Makoto Yokoyama ,  Yoshihiro Takada ,  Keiichi Honma ,  Osamu Kawasaki ,  Masayosi Inoue ,  Kazunari Sugai ,  Jun Tazawa

IPC: F04D29/30 ,  F04D29/66 ,  F24F1/00 ,  F24F3/16 ,  B01D35/30 ,  F01D5/22

CPC classification number: F24F3/1603 ,  F04D29/30 ,  F04D29/662 ,  F24F2001/0096

Abstract: An air cleaner includes a housing having an upper wall and side walls, an air filter mounted with respect to the housing, a fan including a vane-wheel having a plurality of vanes, a supporting plate extending substantially between at least two side walls for supporting the fan. An air flow directional member directs an air flow output from the fan. The vane is formed to have a winglike cross-section, and the vane-wheel includes not more than four vanes. The vane-wheel has a base plate and a shroud. Each of the base plate and the shroud is formed to have a reinforcement portion on its circumference. A U-shaped balance weight is attached to a flattened portion formed on the curled portion. The air cleaner of the present invention can reduce noise and vibration and improve efficiency of the fan.

Abstract translation: 空气净化器包括具有上壁和侧壁的壳体，相对于壳体安装的空气过滤器，包括具有多个叶片的叶轮的风扇，基本上在至少两个侧壁之间延伸的支撑板，用于支撑 风扇。 气流定向构件引导从风扇输出的空气流。 叶片形成为具有翼状横截面，并且叶轮包括不超过四个叶片。 叶轮具有底板和护罩。 基板和护罩中的每一个形成为在其圆周上具有加强部分。 U形平衡重附着在形成在卷曲部分上的扁平部分上。 本发明的空气滤清器可以降低噪音和振动，提高风扇的效率。

公开(公告)号：US09336740B2

公开(公告)日：2016-05-10

申请号：US14127525

申请日：2012-06-26

Applicant: Shige Furuta ,  Yuhichiroh Murakami ,  Makoto Yokoyama ,  Seijirou Gyouten

Inventor： Shige Furuta ,  Yuhichiroh Murakami ,  Makoto Yokoyama ,  Seijirou Gyouten

IPC: G11C19/28 ,  G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.

Abstract translation: 公开了一种移位寄存器，其在各个阶段包括单元电路（11），每个单元电路（11）包括（i）包括第一和第二CMOS电路的触发器（11a）和（ii）用于产生输出的信号生成电路 信号（SROUTk），其使用触发器（11a）的输出（Q，QB），所述移位寄存器包括在所述触发器（11a）的输出晶体管（Tr7）的栅极端之间的浮动控制电路（11c） 信号发生电路（11b）和Q端子。 这使得可以在不引起移位寄存器故障的情况下减小显示驱动电路的电路规模。