公开(公告)号：US20150212849A1

公开(公告)日：2015-07-30

申请号：US14602857

申请日：2015-01-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae Jin LEE ,  Young Su KWON

IPC: G06F9/46

CPC classification number: G06F9/461 ,  G06F9/455

Abstract: Provided are an apparatus and method for multicore emulation based on dynamic context switching. The apparatus for multicore emulation based on dynamic context switching includes a multicore emulation managing unit configured to transmit a signal for requesting determination of a core to be emulated among a plurality of cores, and a context switching managing unit configured to receive the signal for requesting determination of a core to be emulated from the multicore emulation managing unit, determine an ID of a core to be emulated according to the received signal, and executing emulation on a core corresponding to the determined core ID.

Abstract translation: 提供了一种基于动态上下文切换的多核仿真的装置和方法。 基于动态上下文切换的多核心仿真装置包括：多核仿真管理单元，被配置为发送用于请求确定要在多个核心中仿真的核心的信号;以及上下文切换管理单元，被配置为接收用于请求确定的信号 要从多核仿真管理单元仿真的核心，根据接收到的信号确定要仿真的核心的ID，以及对与所确定的核心ID相对应的核心执行仿真。

公开(公告)号：US20150201205A1

公开(公告)日：2015-07-16

申请号：US14595959

申请日：2015-01-13

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae Jin LEE

IPC: H04N19/423 ,  H04N19/187 ,  G06F12/08

CPC classification number: H04N19/423 ,  G06F12/0875

Abstract: Provided are a video decoding apparatus using a frame cache, and a video decoding method performed by the same. The video decoding apparatus includes an address decoding unit configured to determine an area of a memory to be accessed by a processor core based on an address of the memory received from the processor core, a data cache unit configured to cache data required to decode a video in a cache memory operating in conjunction with a data memory so that the processor core accesses an area of the data memory, and a frame cache unit configured to cache frames of the video in the cache memory operating in conjunction with a frame memory so that the processor core accesses an area of the frame memory. Therefore, a delay caused by a cache clear is minimized, so that the performance of a video decoding system can be improved.

Abstract translation: 提供一种使用帧高速缓存的视频解码装置及其执行的视频解码方法。 视频解码装置包括：地址解码单元，被配置为基于从处理器核心接收的存储器的地址来确定要由处理器核心访问的存储器的区域;数据高速缓存单元，被配置为缓存解码视频所需的数据 在与数据存储器结合操作的高速缓存存储器中，使得处理器核心访问数据存储器的区域，以及帧高速缓存单元，其被配置为缓存与帧存储器一起操作的高速缓冲存储器中的视频帧，使得 处理器核心访问帧存储器的区域。 因此，由缓存清除引起的延迟最小化，从而可以提高视频解码系统的性能。