公开(公告)号：US08296256B2

公开(公告)日：2012-10-23

申请号：US12579442

申请日：2009-10-15

Applicant: Eli Arbel ,  Oleg Rokhlenko ,  Karen Yorav

Inventor： Eli Arbel ,  Oleg Rokhlenko ,  Karen Yorav

IPC: G06N7/06 ,  G06F17/50

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F17/505 ,  G06F2217/62 ,  Y02D10/128

Abstract: Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.

Abstract translation: 时钟门控电路通过将时钟门控机会功能转换为非布尔函数并约束非布尔函数的输入来确定。 非布尔函数可以是三元函数。 可以通过引入控制变量和与其值相关联的基数约束来实现约束输入。 可以使用非布尔函数来近似分配有非布尔值的输入的通用量化，例如不关心价值。 可以使用非布尔函数来使用SAT求解器来提供布尔函数的ALL SAT解。

公开(公告)号：US20110093431A1

公开(公告)日：2011-04-21

申请号：US12579442

申请日：2009-10-15

Applicant: Eli Arbel ,  Oleg Rokhlenko ,  Karen Yorav

Inventor： Eli Arbel ,  Oleg Rokhlenko ,  Karen Yorav

IPC: G06N7/00

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F17/505 ,  G06F2217/62 ,  Y02D10/128

Abstract: Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.

Abstract translation: 时钟门控电路通过将时钟门控机会功能转换为非布尔函数并约束非布尔函数的输入来确定。 非布尔函数可以是三元函数。 可以通过引入控制变量和与其值相关联的基数约束来实现约束输入。 可以使用非布尔函数来近似用非布尔值分配的输入的通用量化，例如“不关心”值。 可以使用非布尔函数来使用SAT求解器来提供布尔函数的ALL SAT解。

公开(公告)号：US20120144352A1

公开(公告)日：2012-06-07

申请号：US12957420

申请日：2010-12-01

Applicant: Eli Arbel ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Oleg Rokhlenko

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

公开(公告)号：US20120192130A1

公开(公告)日：2012-07-26

申请号：US13429466

申请日：2012-03-26

Applicant: Eli Arbel ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Oleg Rokhlenko

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract translation: 可以获得并处理响应输入信号的电路设计。 电路设计可以定义组合元件，存储元件和输入信号之间的连接。 可以相对于预定的组合逻辑输入信号来执行截止点的识别。 截止点可以是其值不依赖于预定的组合逻辑输入信号的值的连接。 可以通过放松与截止点相关联的逻辑来合成近似电路设计。 基于近似的电路设计，可以进行处理。 在一些示例性实施例中，存储器元件的时钟门控功能可以通过相对于存储器元件的输出信号近似电路设计来确定。 时钟门控功能可以基于近似的电路设计确定并被引入到电路设计中，有或没有额外的细化。

公开(公告)号：US08166444B2

公开(公告)日：2012-04-24

申请号：US12489441

申请日：2009-06-23

Applicant: Eli Arbel ,  Cindy Eisner ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Cindy Eisner ,  Oleg Rokhlenko

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5068 ,  G06F2217/78

Abstract: An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design.

Abstract translation: 初始时钟门控功能引入原始电路设计。 使用抽象精炼，修改初始时钟门控功能，使门控电路设计相当于原始电路设计。 可以使用诸如SAT求解器的模型检查器来确定两个电路设计的等效性。 对照示例可以由模型检查器确定以否定等效性。 可以利用该示例来修改初始时钟选通功能，以确定等同于原始电路设计的改进的门控电路设计。

公开(公告)号：US08166426B2

公开(公告)日：2012-04-24

申请号：US12191732

申请日：2008-08-14

Applicant: Eli Arbel ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Oleg Rokhlenko

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A method for reducing a depth of binary decision diagram includes identifying, with a processing device, one or more less probable positive paths within the binary decision diagram, the less probable positive paths within the binary decision diagram include a number of decision nodes from a starting variable to a positive, binary logic “1” terminal node within the binary decision diagram, and the identified less probable positive paths are eliminated. Identifying the less probable positive paths within the binary decision diagram includes: assigning ƒ to the binary decision diagram, assigning K to a depth threshold of the binary decision diagram, and constructing a second binary decision diagram g by logically ORing together positive paths in ƒ that have a length above K. Eliminating the identified less probable positive paths in ƒ comprises obtaining an approximated function ƒ′, by conjuncting ƒ and the negation of g, such that ƒ′≡ƒ^ g.

Abstract translation: 一种用于减少二进制判定图的深度的方法包括：利用处理设备来识别二进制判定图内的一个或多个较少可能的正向路径，二进制判定图中的可能的正向路径越少，包括起始处的多个决策节点 变量为二进制判定图中的正二进制逻辑“1”终端节点，并且识别出较不可能的正路径被消除。 识别二进制决策图中较不可能的正向路径包括：将二进制决策图分配给二进制决策图的深度阈值，并将第二个二进制决策图g逻辑地与 长度大于K.消除在ƒ中识别的较不可能的正路径包括通过连接f和g的否定获得近似函数ƒ'，使得ƒ'≡ƒ^ g。

公开(公告)号：US20100325596A1

公开(公告)日：2010-12-23

申请号：US12489441

申请日：2009-06-23

Applicant: Eli Arbel ,  Cindy Eisner ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Cindy Eisner ,  Oleg Rokhlenko

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/78

Abstract: An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design.

Abstract translation: 初始时钟门控功能引入原始电路设计。 使用抽象精炼，修改初始时钟门控功能，使门控电路设计相当于原始电路设计。 可以使用诸如SAT求解器的模型检查器来确定两个电路设计的等效性。 对照示例可以由模型检查器确定以否定等效性。 可以利用该示例来修改初始时钟选通功能，以确定等同于原始电路设计的改进的门控电路设计。

公开(公告)号：US08539403B2

公开(公告)日：2013-09-17

申请号：US13175854

申请日：2011-07-03

Applicant: Eli Arbel ,  Cynthia Rae Eisner ,  Oleg Rokhlenko ,  Karen Frida Yorav

Inventor： Eli Arbel ,  Cynthia Rae Eisner ,  Oleg Rokhlenko ,  Karen Frida Yorav

IPC: G06F9/455

CPC classification number: G06F17/505 ,  G06F2217/14

Abstract: A method, apparatus and computer program product for modifying a circuit design. The method comprising: obtaining a design of a circuit, the design comprising at least a first memory element and a second memory element. The method further comprising selecting the second memory element to be a dominant memory element over the first memory element. The method further comprising modifying the design of the circuit by replacing usage of an output signal of the first memory element with usage of an output signal of the dominant memory element in one or more cycles in which values of the output signals of the first memory element and the dominant memory element are equal. Whereby a reduction in observabiltiy of the first memory element in the design is achieved.

Abstract translation: 一种用于修改电路设计的方法，装置和计算机程序产品。 该方法包括：获得电路的设计，该设计包括至少第一存储器元件和第二存储器元件。 所述方法还包括：通过所述第一存储器元件选择所述第二存储器元件作为主要存储器元件。 该方法还包括通过在一个或多个周期内替换使用主存储器元件的输出信号的第一存储元件的输出信号的使用来替换电路的设计，其中第一存储元件的输出信号的值 而显存存储元件相等。 从而实现了设计中第一个存储元件的可观察性的减少。

公开(公告)号：US08261227B2

公开(公告)日：2012-09-04

申请号：US12957420

申请日：2010-12-01

Applicant: Eli Arbel ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Oleg Rokhlenko

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract translation: 可以获得并处理响应输入信号的电路设计。 电路设计可以定义组合元件，存储元件和输入信号之间的连接。 可以相对于预定的组合逻辑输入信号来执行截止点的识别。 截止点可以是其值不依赖于预定的组合逻辑输入信号的值的连接。 可以通过放松与截止点相关联的逻辑来合成近似电路设计。 基于近似的电路设计，可以进行处理。 在一些示例性实施例中，存储器元件的时钟门控功能可以通过相对于存储器元件的输出信号近似电路设计来确定。 时钟门控功能可以基于近似的电路设计确定并被引入到电路设计中，有或没有额外的细化。

公开(公告)号：US08713509B2

公开(公告)日：2014-04-29

申请号：US13429466

申请日：2012-03-26

Applicant: Eli Arbel ,  Oleg Rokhlenko

Inventor： Eli Arbel ,  Oleg Rokhlenko

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/505 ,  G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

Abstract: A circuit design, responsive the input signals, may be obtained and processed. The circuit design may define connections between combinational elements, memory elements, and input signals. Identification of cut-off points may be performed with respect to predetermined combinational logic input signals. The cut-off points may be connections whose values are not dependant on the value of the predetermined combinational logic input signals. An approximated circuit design may be synthesized by relaxing the logic associated with the cut-off points. Based on the approximated circuit design, processing may be performed. In some exemplary embodiments, a clock gating function of a memory element may be determined by approximating the circuit design with respect to the output signal of the memory element. The clock gating function may be determined based on the approximated circuit design and introduced to the circuit design, with or without additional refinement.

Abstract translation: 可以获得并处理响应输入信号的电路设计。 电路设计可以定义组合元件，存储元件和输入信号之间的连接。 可以相对于预定的组合逻辑输入信号来执行截止点的识别。 截止点可以是其值不依赖于预定的组合逻辑输入信号的值的连接。 可以通过放松与截止点相关联的逻辑来合成近似电路设计。 基于近似的电路设计，可以进行处理。 在一些示例性实施例中，存储器元件的时钟门控功能可以通过相对于存储器元件的输出信号近似电路设计来确定。 时钟门控功能可以基于近似的电路设计确定并被引入到电路设计中，有或没有额外的细化。