公开(公告)号：US20220139479A1

公开(公告)日：2022-05-05

申请号：US17088608

申请日：2020-11-04

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Yu-Tao Lin ,  Tse-Hua Yao ,  Yi-Fan Chen

IPC: G11C29/38 ,  G06F3/06 ,  G11C8/06

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

公开(公告)号：US11335427B1

公开(公告)日：2022-05-17

申请号：US17088608

申请日：2020-11-04

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Yu-Tao Lin ,  Tse-Hua Yao ,  Yi-Fan Chen

IPC: G11C8/06 ,  G11C29/38 ,  G06F3/06

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.