公开(公告)号：US20150242128A1

公开(公告)日：2015-08-27

申请号：US14371706

申请日：2013-12-09

Applicant: Empire Technology Development LLC

Inventor： Mordehai Margalit ,  David Hirshberg ,  Netzer Moriya

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/0658 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F2003/0692

Abstract: Technologies are generally described to establish a hardware interconnect based communication between SSD controllers. According to some examples, a first solid state drive (SSD) controller and a second SSD controller are detected. The hardware interconnect is detected between the first SSD controller and the second SSD controller. Next, a communication connection between the first SSD controller and the second SSD controller is established through the hardware interconnect. The first SSD controller may be allowed to manage a flash controller of the second SSD controller for tasks that include a deduplication task and a low level redundant array of independent disks (RAID) task.

Abstract translation: 通常描述技术来建立SSD控制器之间的基于硬件互连的通信。 根据一些示例，检测到第一固态驱动器（SSD）控制器和第二SSD控制器。 在第一SSD控制器和第二SSD控制器之间检测硬件互连。 接下来，通过硬件互连建立第一SSD控制器和第二SSD控制器之间的通信连接。 可以允许第一SSD控制器管理第二SSD控制器的闪存控制器，用于包括重复数据删除任务和独立磁盘（RAID）任务的低级冗余阵列的任务。

公开(公告)号：US09898195B2

公开(公告)日：2018-02-20

申请号：US14371706

申请日：2013-12-09

Applicant: Empire Technology Development LLC

Inventor： Mordehai Margalit ,  David Hirshberg ,  Netzer Moriya

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0641 ,  G06F3/0658 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F2003/0692

Abstract: Technologies are generally described to establish a hardware interconnect based communication between SSD controllers. According to some examples, a first solid state drive (SSD) controller and a second SSD controller are detected. The hardware interconnect is detected between the first SSD controller and the second SSD controller. Next, a communication connection between the first SSD controller and the second SSD controller is established through the hardware interconnect. The first SSD controller may be allowed to manage a flash controller of the second SSD controller for tasks that include a deduplication task and a low level redundant array of independent disks (RAID) task.