公开(公告)号：US20070115039A1

公开(公告)日：2007-05-24

申请号：US11287550

申请日：2005-11-22

申请人： Erich Lowe ,  Michael May

发明人： Erich Lowe ,  Michael May

IPC分类号： G06F1/04

CPC分类号： G06F1/06

摘要： A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.

摘要翻译： 片上集成电路系统包括第一电路模块和N个其它电路模块，其可操作以基于至少一个输入信号产生至少一个输出信号。 用于产生第一电路模块的基本时钟信号的参考振荡器。 时钟延迟发生器以相应的N个时钟延迟产生N个延迟时钟信号，其中N大于或等于2.N个延迟的时钟信号提供给N个其他电路模块。

公开(公告)号：US20070160167A1

公开(公告)日：2007-07-12

申请号：US11328830

申请日：2006-01-09

申请人： Michael May ,  Erich Lowe

发明人： Michael May ,  Erich Lowe

IPC分类号： H04L27/00

CPC分类号： H04B1/406 ,  H03D5/00 ,  H04B1/0003

摘要： An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.

摘要翻译： 一种集成电路包括用于接收具有多个信道信号的接收无线电信号的无线电接收机，多个信道信号中的每一个被以相应的多个载频中的一个调制。 无线电接收机将所选择的多个信道信号转换为解调信号。 接口时钟发生器以基于多个信道信号中选择的一个信道信号而变化的第一接口时钟频率生成第一接口时钟。 第一接口时钟频率和第一时钟频率的整数倍基本上不等于多个信道信号中所选择的一个的载波频率。 驱动器模块基于第一接口时钟驱动与设备的设备接口。

公开(公告)号：US20070116147A1

公开(公告)日：2007-05-24

申请号：US11287551

申请日：2005-11-22

申请人： Michael May ,  Erich Lowe

发明人： Michael May ,  Erich Lowe

IPC分类号： H04L27/00

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period. The plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;

摘要翻译： 片上集成电路系统包括第一数字模块和第二数字模块，使得第二数字模块在预定时段期间产生基于在先前预定周期期间产生的第一数字模块的输出的输出。 数字时钟发生器在预定周期内生成具有多个第一数字时钟周期的基本时钟信号和在预定周期内具有多个第二数字时钟周期的第二数字时钟信号。 多个第一数字时钟周期在预定周期内与多个第二数字时钟周期基本交错;

公开(公告)号：US20070165747A1

公开(公告)日：2007-07-19

申请号：US11287549

申请日：2005-11-22

申请人： Michael May ,  Erich Lowe

发明人： Michael May ,  Erich Lowe

IPC分类号： H04L27/00

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.

摘要翻译： 数字时钟发生器包括基本时钟发生器，用于响应于控制信号而以可变的基本时钟频率产生基本时钟信号。 数字时钟控制器在预定时间段内产生具有基本恒定数量的时钟周期数的数字时钟信号。

公开(公告)号：US20070116148A1

公开(公告)日：2007-05-24

申请号：US11287571

申请日：2005-11-22

申请人： Erich Lowe ,  Michael May

发明人： Erich Lowe ,  Michael May

IPC分类号： H04L27/00

CPC分类号： H04B15/02 ,  H04B2215/065

摘要： A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

摘要翻译： 片上集成电路系统包括：模拟前端，用于接收具有多个信道信号的接收无线电信号，多个信道信号中的每一个以对应的多个载波频率中的一个调制，并且用于将所选择的一个 的多个信道信号转换为数字信号。 数字时钟发生器以数字时钟频率产生数字时钟信号，该数字时钟频率根据所选择的多个信道信号之一而变化。 数字时钟频率和数字时钟频率的整数倍基本上不等于多个信道信号中所选择的一个的载波频率。 数字部分基于数字时钟信号将数字信号转换成对应于多个信道中所选择的一个信道的至少一个音频信号。

公开(公告)号：US20070116150A1

公开(公告)日：2007-05-24

申请号：US11287570

申请日：2005-11-22

申请人： Michael May ,  Erich Lowe

发明人： Michael May ,  Erich Lowe

IPC分类号： H03D3/00

CPC分类号： H03D3/007 ,  H03J1/0008

摘要： A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

摘要翻译： 一种片上集成电路系统包括第一同相数字子模块和第一正交相位数字子模块，使得第一同相数字子模块和第一正交相位数字子模块可操作以基于at产生至少一个输出信号 至少一个输入信号。 数字时钟发生器产生具有在预定周期内具有多个第一同相数字时钟周期的第一同相数字时钟信号和在预定周期内具有多个第一正交相位数字时钟周期的第一正交相位数字时钟信号 。 多个第一同相数字时钟周期在预定周期内与多个第一正交相位数字时钟周期基本交错。

公开(公告)号：US20070115161A1

公开(公告)日：2007-05-24

申请号：US11287572

申请日：2005-11-22

申请人： Michael May ,  Erich Lowe

发明人： Michael May ,  Erich Lowe

IPC分类号： H03M1/12

CPC分类号： H04B15/02 ,  H04B2215/065 ,  H04H40/18

摘要： A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.

摘要翻译： 片上集成电路系统包括第一数字模块第二数字模块，使得第一数字模块和第二数字模块可操作地耦合以基于输入信号基于第一数字时钟信号和 第二数字时钟信号。 数字时钟发生器以基于时钟频率的基本时钟信号产生基于控制信号而变化的基本时钟信号，并且产生在预定时段内具有基本上恒定数量的第一数字时钟周期的第一数字时钟信号，并产生第二数字时钟信号 在预定时段内具有基本恒定数量的第二数字时钟周期。

公开(公告)号：US07323921B2

公开(公告)日：2008-01-29

申请号：US11287550

申请日：2005-11-22

申请人： Erich Lowe ,  Michael R. May

发明人： Erich Lowe ,  Michael R. May

IPC分类号： G06F1/04

CPC分类号： G06F1/06

摘要： A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.

摘要翻译： 片上集成电路系统包括第一电路模块和N个其他电路模块，其可操作以基于至少一个输入信号产生至少一个输出信号。 用于产生第一电路模块的基本时钟信号的参考振荡器。 时钟延迟发生器以相应的N个时钟延迟产生N个延迟时钟信号，其中N大于或等于2.N个延迟的时钟信号提供给N个其他电路模块。

公开(公告)号：US07672403B2

公开(公告)日：2010-03-02

申请号：US11287570

申请日：2005-11-22

申请人： Michael R. May ,  Erich Lowe

发明人： Michael R. May ,  Erich Lowe

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H03D3/007 ,  H03J1/0008

摘要： A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

摘要翻译： 一种片上集成电路系统包括第一同相数字子模块和第一正交相位数字子模块，使得第一同相数字子模块和第一正交相位数字子模块可操作以基于at产生至少一个输出信号 至少一个输入信号。 数字时钟发生器产生具有在预定周期内具有多个第一同相数字时钟周期的第一同相数字时钟信号和在预定周期内具有多个第一正交相位数字时钟周期的第一正交相位数字时钟信号 。 多个第一同相数字时钟周期在预定周期内与多个第一正交相位数字时钟周期基本交错。

公开(公告)号：US07620131B2

公开(公告)日：2009-11-17

申请号：US11287549

申请日：2005-11-22

申请人： Michael R. May ,  Erich Lowe

发明人： Michael R. May ,  Erich Lowe

IPC分类号： H04B1/10

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.

摘要翻译： 数字时钟发生器包括基本时钟发生器，用于响应于控制信号而以可变的基本时钟频率产生基本时钟信号。 数字时钟控制器在预定时间段内产生具有基本恒定数量的时钟周期数的数字时钟信号。