公开(公告)号：US11303289B2

公开(公告)日：2022-04-12

申请号：US17002967

申请日：2020-08-26

Applicant: Eridan Communications, Inc.

Inventor： Richard W. D. Booth

IPC: H03L7/24 ,  G06F1/02 ,  H03M9/00 ,  G06F1/03

Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate fCLK, to produce a full-speed serialized digital output having 2n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency fOUT=(M/2n)×fCLK.

公开(公告)号：US10763873B1

公开(公告)日：2020-09-01

申请号：US16746690

申请日：2020-01-17

Applicant: Eridan Communications, Inc.

Inventor： Richard W. D. Booth

IPC: H03L7/24 ,  G06F1/02 ,  H03M9/00 ,  G06F1/03

Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate fCLK, to produce a full-speed serialized digital output having 2n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency fOUT=(M/2n)×fCLK.