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公开(公告)号：US20240106464A1
公开(公告)日：2024-03-28
申请号：US17934758
申请日：2022-09-23
Applicant: Eridan Communications, Inc.
Inventor： Hazal Yüksel , Douglas Kirkpatrick , Dubravko Babic
CPC classification number: H04B1/006 , H04B1/10 , H04B1/30 , H04B2001/307
Abstract: A wideband-tunable radio frequency (RF) receiver having a tunable RF bandpass filter (RF BPF) and passive mixer-first receiver (PMF-Rx) is disclosed. The tunable RF BPF and PMF-Rx operate synergistically, exploiting the intrinsic impedance translation property of the PMF-Rx, to suppress out-of-band interferers as well as in-band interferers at the receiver front end and thereby enhance the receiver's signal-to-noise ratio and overall dynamic range. In one embodiment of the invention the tunable RF BPF and PMF-Rx are independently tunable and afford the receiver the ability to reject or suppress interferers that might not otherwise be able to be rejected or suppressed.
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公开(公告)号：US20220368368A1
公开(公告)日：2022-11-17
申请号：US17813267
申请日：2022-07-18
Applicant: Eridan Communications, Inc.
Inventor： Douglas A. Kirkpatrick , Earl W. McCune, JR.
Abstract: A universal transmit-receive (UTR) module for phased array systems comprises an antenna element shared for both transmitting and receiving; a transmit path that includes a transmit-path phase shifter, a driver, a switch-mode power amplifier (SMPA) that is configured to be driven by the driver, and a dynamic power supply (DPS) that generates and supplies a DPS voltage to the power supply port of the SMPA; and a receive path that includes a TX/RX switch that determines whether the receive path is electrically connected to or electrically isolated from the antenna element, a bandpass filter (BPF) that aligns with the intended receive frequency and serves to suppress reflected transmit signals and reverse signals, an adjustable-gain low-noise amplifier (LNA), and a receive-path phase shifter. The UTR module is specially designed for operation in phased array systems. The versatility and wideband agility of the UTR module allows a single phased array system to be designed that can be used for multiple purposes, such as, for example, both radar and communications applications.
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公开(公告)号：US20210337654A1
公开(公告)日：2021-10-28
申请号：US17369676
申请日：2021-07-07
Applicant: Eridan Communications, Inc.
Inventor： Douglas A. Kirkpatrick , Quentin Diduck
IPC: H05K1/02 , H01L23/367 , H05K7/20 , H05K3/30
Abstract: An integrated circuit printed circuit board (IC-PCB) assembly comprises a PCB and a heatsink plate. The PCB has a first side including a first patterned conductive layer with one or more thermal pads onto which one or more heat slugs of one or more ICs mount, and a second, opposing side including a second patterned conductive layer with a heatsink plate receiving pad onto which the heatsink plate mounts. The heatsink plate has one or more posts that project from a mounting surface of the heatsink plate, and when the heatsink plate is mounted to the heatsink plate receiving pad, each post extends from the second side of the PCB, through a matching hole in the PCB, and to an associated thermal pad located on the first side of the PCB.
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公开(公告)号：US09806678B2
公开(公告)日：2017-10-31
申请号：US14754656
申请日：2015-06-29
Applicant: Eridan Communications, Inc.
Inventor： Quentin Diduck
CPC classification number: H03F1/42 , H03F1/0205 , H03F1/0233 , H03F3/193 , H03F3/2173 , H03F2200/351 , H03F2200/36 , H03F2200/451
Abstract: A high-power, high-frequency radio frequency power amplifier includes an output stage and a single-phase driver. The output stage is arranged in a Class-D amplifier configuration and includes a first depletion mode field effect transistor (FET), a second depletion mode FET, and a bootstrap path that couples the output of the output stage to the gate of the second FET. The first and second depletion mode FETs are switched out-of-phase and between fully-ON and fully-OFF states, under the direction of the single-phase driver. The single-phase driver directly controls the ON/OFF state of the first depletion mode FET and provides a discharge path through which the input gate capacitor of the second depletion mode FET in the output stage can discharge to turn OFF the second depletion mode FET. The bootstrap path provides a current path through which the input gate capacitor of the second depletion mode FET can charge to turn the second depletion mode FET ON.
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公开(公告)号：US20160294341A1
公开(公告)日：2016-10-06
申请号：US15182522
申请日：2016-06-14
Applicant: Eridan Communications, Inc.
Inventor： Earl W. McCune, JR.
CPC classification number: H03F3/2171 , H03F1/0283 , H03F1/301 , H03F1/3205 , H03F3/193 , H03F3/195 , H03F3/45179 , H03F3/45183 , H03F3/45381 , H03F2200/451 , H03F2203/45112 , H03G1/0029
Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. To maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.
Abstract translation: 开关模式RFPA驱动器包括以图腾柱状配置布置的第一和第二场效应晶体管（FET）。 开关模式RFPA驱动器用于从具有大致正弦波状波形的输入RF信号产生具有大致方波形波形的开关模式RFPA驱动信号。 为了最大化高频操作并避免开关模式RFPA驱动信号失真，开关模式RFPA驱动器被设计成使其输出可以直接连接到要驱动的开关模式RFPA的输入端，即不使用 或需要使用交流耦合电容器。 开关模式RFPA驱动器的第一个和第二个FET被设计和配置为将开关模式RFPA驱动信号的上限和下限幅度电平限制和控制到适合直接切换开关模式RFPA的电平，从而避免任何需要 直流偏置在开关模式RFPA的输入端。
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Patent Agency Ranking
公开(公告)号：US09397621B2
公开(公告)日：2016-07-19
申请号：US14447452
申请日：2014-07-30
Applicant: Eridan Communications, Inc.
Inventor： Earl W McCune, Jr.
CPC classification number: H03F3/2171 , H03F1/0283 , H03F1/301 , H03F1/3205 , H03F3/193 , H03F3/195 , H03F3/45179 , H03F3/45183 , H03F3/45381 , H03F2200/451 , H03F2203/45112 , H03G1/0029
Abstract: A switch-mode RFPA driver includes first and second field-effect transistors (FETs) arranged in a totem-pole-like configuration. The switch-mode RFPA driver operates to generate a switch-mode RFPA drive signal having a generally square-wave-like waveform from an input RF signal having a generally sinusoidal-like waveform. To maximize high-frequency operation and avoid distorting the switch-mode RFPA drive signal, the switch-mode RFPA driver is designed so that its output can be connected directly to the input of the switch-mode RFPA to be driven, i.e., without using or requiring the use of an AC coupling capacitor. The first and second FETs of the switch-mode RFPA driver are designed and configured to limit and control the upper and lower magnitude levels of the switch-mode RFPA drive signal to levels suitable for switching the switch-mode RFPA directly, obviating any need for DC biasing at the input of the switch-mode RFPA.
Abstract translation: 开关模式RFPA驱动器包括以图腾柱状配置布置的第一和第二场效应晶体管（FET）。 开关模式RFPA驱动器用于从具有大致正弦波状波形的输入RF信号产生具有大致方波形波形的开关模式RFPA驱动信号。 为了最大化高频操作并避免开关模式RFPA驱动信号失真，开关模式RFPA驱动器被设计成使得其输出可以直接连接到要驱动的开关模式RFPA的输入端，即不使用 或需要使用交流耦合电容器。 开关模式RFPA驱动器的第一和第二FET被设计和配置为将开关模式RFPA驱动信号的上限和下限幅度电平限制和控制到适合于直接切换开关模式RFPA的电平，从而避免了 直流偏置在开关模式RFPA的输入端。
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公开(公告)号：US11303289B2
公开(公告)日：2022-04-12
申请号：US17002967
申请日：2020-08-26
Applicant: Eridan Communications, Inc.
Inventor： Richard W. D. Booth
Abstract: A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency fCLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate fCLK, to produce a full-speed serialized digital output having 2n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency fOUT=(M/2n)×fCLK.
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公开(公告)号：US11038466B2
公开(公告)日：2021-06-15
申请号：US16544172
申请日：2019-08-19
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
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公开(公告)号：US20210058035A1
公开(公告)日：2021-02-25
申请号：US16544172
申请日：2019-08-19
Applicant: Eridan Communications, Inc.
Inventor： Waclaw Godycki
Abstract: A wideband envelope modulator comprises a direct current (DC)-to-DC switching converter connected in series with a linear amplitude modulator (LAM). The DC-DC switching converter includes a pulse-width modulator that generates a PWM signal with modulated pulse widths representing a time varying magnitude of an input envelope signal or a pulse-density modulator that generates a PDM signal with a modulated pulse density representing the time varying magnitude of the input envelope signal, a field-effect transistor (FET) driver stage that generates a PWM or PDM drive signal, a high-power output switching stage that is driven by the PWM or PDM drive signal, and an output energy storage network including a low-pass filter (LPF) of order greater than two that filters a switching voltage produced at an output switching node of the high-power output switching stage.
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公开(公告)号：US20200304166A1
公开(公告)日：2020-09-24
申请号：US16871899
申请日：2020-05-11
Applicant: Eridan Communications, Inc.
Inventor： Douglas A. Kirkpatrick , Earl W. McCune, JR.
Abstract: A universal transmit-receive (UTR) module for phased array systems comprises an antenna element shared for both transmitting and receiving; a transmit path that includes a transmit-path phase shifter, a driver, a switch-mode power amplifier (SMPA) that is configured to be driven by the driver, and a dynamic power supply (DPS) that generates and supplies a DPS voltage to the power supply port of the SMPA; and a receive path that includes a TX/RX switch that determines whether the receive path is electrically connected to or electrically isolated from the antenna element, a bandpass filter (BPF) that aligns with the intended receive frequency and serves to suppress reflected transmit signals and reverse signals, an adjustable-gain low-noise amplifier (LNA), and a receive-path phase shifter. The UTR module is specially designed for operation in phased array systems. The versatility and wideband agility of the UTR module allows a single phased array system to be designed that can be used for multiple purposes, such as, for example, both radar and communications applications.
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