公开(公告)号：US07197446B2

公开(公告)日：2007-03-27

申请号：US10711168

申请日：2004-08-30

申请人： Erik Breiland ,  Timothy W. Budell ,  Charles S. Chiu ,  Paul L. Clouser ,  Charles K. Erdelyi ,  Brian P. Welch

发明人： Erik Breiland ,  Timothy W. Budell ,  Charles S. Chiu ,  Paul L. Clouser ,  Charles K. Erdelyi ,  Brian P. Welch

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

摘要翻译： 本发明一般涉及一种用于产生与微电子封装特别相关的频率相关的电气模型的电源噪声和信号完整性分析方法。 该方法公开了在典型芯片封装中遇到的几何形状的等效电路的创建，包括如何将几何划分成小于小于最小波长（λ）的1/20的单元，以及如何处理信号和电源通孔， 信号线和电源平面。 该方法还指示如何为每个等效电路中的每个电感器，电容器，电阻器和传输线分配值。 该方法还提供仅在相邻小区之间发生的那些相互作用的建模。

公开(公告)号：US20100005435A1

公开(公告)日：2010-01-07

申请号：US12166550

申请日：2008-07-02

申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

公开(公告)号：US08234611B2

公开(公告)日：2012-07-31

申请号：US12166550

申请日：2008-07-02

申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

公开(公告)号：US08510697B2

公开(公告)日：2013-08-13

申请号：US13448925

申请日：2012-04-17

申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

公开(公告)号：US20060047490A1

公开(公告)日：2006-03-02

申请号：US10711168

申请日：2004-08-30

申请人： Erik Breiland ,  Timothy Budell ,  Charles Chiu ,  Paul Clouser ,  Charles Erdelyi ,  Brian Welch

发明人： Erik Breiland ,  Timothy Budell ,  Charles Chiu ,  Paul Clouser ,  Charles Erdelyi ,  Brian Welch

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

摘要翻译： 本发明一般涉及一种用于产生与微电子封装特别相关的频率相关的电气模型的电源噪声和信号完整性分析方法。 该方法公开了在典型芯片封装中遇到的几何形状的等效电路的创建，包括如何将几何划分成小于小于最小波长（λ）的1/20的单元，以及如何处理信号和电源通孔， 信号线和电源平面。 该方法还指示如何为每个等效电路中的每个电感器，电容器，电阻器和传输线分配值。 该方法还提供仅在相邻小区之间发生的那些相互作用的建模。