公开(公告)号：US08234611B2

公开(公告)日：2012-07-31

申请号：US12166550

申请日：2008-07-02

申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

公开(公告)号：US08510697B2

公开(公告)日：2013-08-13

申请号：US13448925

申请日：2012-04-17

申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

公开(公告)号：US20100005435A1

公开(公告)日：2010-01-07

申请号：US12166550

申请日：2008-07-02

申请人： Erik Breiland ,  Charles S. Chiu ,  Prince George

发明人： Erik Breiland ,  Charles S. Chiu ,  Prince George

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

摘要翻译： 本发明一般涉及用于对I / O同时开关噪声进行建模的系统和方法，更具体地说，涉及用于在选择的芯片窗口区域中建模I / O同时开关噪声的系统和方法，同时考虑到邻居之间的电流共享的影响 。 一种方法包括确定集成电路（IC）芯片封装的区域的电流共享因子，以及基于IC的相邻区域中的I / O设备的当前共享因数和数量来确定IC芯片封装的卸载缩放因子 芯片封装。

公开(公告)号：US07197446B2

公开(公告)日：2007-03-27

申请号：US10711168

申请日：2004-08-30

申请人： Erik Breiland ,  Timothy W. Budell ,  Charles S. Chiu ,  Paul L. Clouser ,  Charles K. Erdelyi ,  Brian P. Welch

发明人： Erik Breiland ,  Timothy W. Budell ,  Charles S. Chiu ,  Paul L. Clouser ,  Charles K. Erdelyi ,  Brian P. Welch

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (λ) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

摘要翻译： 本发明一般涉及一种用于产生与微电子封装特别相关的频率相关的电气模型的电源噪声和信号完整性分析方法。 该方法公开了在典型芯片封装中遇到的几何形状的等效电路的创建，包括如何将几何划分成小于小于最小波长（λ）的1/20的单元，以及如何处理信号和电源通孔， 信号线和电源平面。 该方法还指示如何为每个等效电路中的每个电感器，电容器，电阻器和传输线分配值。 该方法还提供仅在相邻小区之间发生的那些相互作用的建模。

公开(公告)号：US06584596B2

公开(公告)日：2003-06-24

申请号：US09682584

申请日：2001-09-24

申请人： Patrick H. Buffet ,  Charles S. Chiu ,  Yu H. Sun

发明人： Patrick H. Buffet ,  Charles S. Chiu ,  Yu H. Sun

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F2217/40

摘要： Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.

摘要翻译： 公开了一种设计用于芯片的焊料凸块封装中的电压隔板的方法，包括：确定芯片电压岛的电流要求，芯片电压岛包括芯片功率和信号焊盘，并创建芯片电压的等效电路模型 岛; 定义封装电压岛，封装电压岛包括电源和信号封装引脚，并创建封装电压岛的等效电路模型; 分析芯片电压岛模型和封装电压岛模型组合的电气属性; 并修改封装电压岛直到电气属性是可接受的。

公开(公告)号：US20090094564A1

公开(公告)日：2009-04-09

申请号：US11866591

申请日：2007-10-03

申请人： Timothy W. Budell ,  Charles S. Chiu ,  David C. Reynolds ,  Eric W. Tremble

发明人： Timothy W. Budell ,  Charles S. Chiu ,  David C. Reynolds ,  Eric W. Tremble

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method for quickly tracing minimum-length conductive return paths through an electronic structure utilizes a raster based (cellular) memory model comprising individual grids for each layer of the structure. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used to determine, for each signal net, the shortest return path. This information can then be used for various purposes, including determining if the return path is sufficient to ensure adequate signal integrity.

摘要翻译： 用于快速跟踪通过电子结构的最小长度导电返回路径的方法利用基于光栅的（蜂窝）存储器模型，其包括用于结构的每个层的各个格栅。 每个网格包括该层上的导电结构的降低分辨率的N×M单元表示。 然后使用蜂窝方法来确定每个信号网络的最短返回路径。 然后，该信息可用于各种目的，包括确定返回路径是否足以确保足够的信号完整性。

公开(公告)号：US07038319B2

公开(公告)日：2006-05-02

申请号：US10644372

申请日：2003-08-20

申请人： Patrick H. Buffet ,  Charles S. Chiu ,  Jon D. Garlett ,  Louis L. Hsu ,  Brian J. Schuh

发明人： Patrick H. Buffet ,  Charles S. Chiu ,  Jon D. Garlett ,  Louis L. Hsu ,  Brian J. Schuh

IPC分类号： H01L23/48

CPC分类号： H01L23/642 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/05599

摘要： A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.

摘要翻译： 公开了一种在载体层中的相邻信号之间的串扰减小的半导体芯片封装。 用于承载第一信号的第一对导体提供在载体的层中。 用于承载第二信号的第二对导体被提供为邻近层中的第一对导体，其中第一和第二对导体被配置为使得第一和第二对导体之间的串扰基本上最小化， 而不会增加包装的尺寸。 第一对导体的高度比第二对导体短。 或者，第一和第二对导体被配置成使得它们彼此均匀地影响。 芯片封装因此减少串扰，而不会影响封装中互连的密度，或导致封装尺寸的增加。

公开(公告)号：US20130054202A1

公开(公告)日：2013-02-28

申请号：US13219813

申请日：2011-08-29

申请人： Kurt A. Carlsen ,  Charles S. Chiu ,  Umberto Garofano ,  Ze Gui Pang ,  Eric W. Tremble ,  David Toub ,  Ivan L. Wemple

发明人： Kurt A. Carlsen ,  Charles S. Chiu ,  Umberto Garofano ,  Ze Gui Pang ,  Eric W. Tremble ,  David Toub ,  Ivan L. Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5063 ,  G06F2217/78 ,  G06F2217/82

摘要： Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.

摘要翻译： 方法，系统，计算机程序等为集成电路的一个区域确定所需数量的去耦电容器和去耦电容器的近似位置。 该区域的切换元件被输入到在计算机化设备上运行的仿真程序中。 此外，该区域的配电模型被输入到模拟程序中，并且将电源电压压缩目标输入到模拟程序中。 当所有开关元件同时切换时，这些方法，系统等产生满足压缩目标所需的去耦电容器的数量。 对于每个开关元件，方法，系统等产生特定数量的去耦电容器，以便在仅元件切换时满足压缩，将特定数量的一部分计算为上限，分配总数的分数 的去耦电容器到每个开关电路元件，并将去耦电容器总数的一部分放置在电气附近的元件上。

公开(公告)号：US20100332193A1

公开(公告)日：2010-12-30

申请号：US12492198

申请日：2009-06-26

申请人： Haitian Hu ,  Timothy W. Budell ,  Charles S. Chiu ,  Eric Tremble

发明人： Haitian Hu ,  Timothy W. Budell ,  Charles S. Chiu ,  Eric Tremble

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H01L23/552 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01076 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate. The method includes: setting parameters related to the IC package layout of groups of bond wires; sub-dividing each group of bond wires into regions, each including a portion of the bond wire or its corresponding pad, and generating dissection planes for the regions consisting of the bond wires; performing a 3D simulation on the regions consisting of the corresponding pads, and a 2D simulation for each dissection plane; constructing equivalent circuit models for groups of bond wires and corresponding pads based on the 3D and 2D simulations results; inputting the equivalent circuit models into a circuit simulator to measure the noise effects; and modifying the layout geometry to meet noise targets.

摘要翻译： 一种用于在IC封装中建模接合线的方法，用于预测复杂接合线配置中由电磁耦合产生的噪声影响。 产生用于接合线的等效LC电路模型的查找表，其精确地预测信号传输系统的接合线电路的影响。 应用开关和镜像技术来减少模拟所需的接合线配置。 该方法包括：设置与电线组IC封装布局有关的参数; 将每组接合线分割成区域，每个区域包括接合线的一部分或其对应的衬垫，并为由接合线组成的区域产生解剖平面; 在由相应的垫组成的区域上进行3D模拟，以及对每个解剖平面进行2D模拟; 基于3D和2D模拟结果构建了用于焊接线组和相应焊盘组的等效电路模型; 将等效电路模型输入到电路模拟器中以测量噪声影响; 并修改布局几何以满足噪声目标。

公开(公告)号：US06584606B1

公开(公告)日：2003-06-24

申请号：US09584416

申请日：2000-06-01

申请人： Charles S. Chiu ,  James P. Libous ,  Rory D. Loughran ,  Joseph Natonio ,  Robert A. Proctor ,  Gulsun Yasar

发明人： Charles S. Chiu ,  James P. Libous ,  Rory D. Loughran ,  Joseph Natonio ,  Robert A. Proctor ,  Gulsun Yasar

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.

摘要翻译： 分析集成电路（例如ASIC）的I / O单元布局的方法包括在所选择的芯片图像上定义所提出的I / O单元布局，为电迁移，IR电压降和di / dt噪声提供一组限制规则 所选择的芯片图像，为所提出的I / O单元布局中使用的每个I / O单元类型提供特征，通过对所提出的I / O单元布局应用限制规则来检查所提出的I / O单元布局，并报告所有I / 在所提出的I / O单元布局中使用的O单元不符合所选芯片图像的限制规则。