Method and apparatus for occlusion culling of graphic objects
    1.
    发明申请
    Method and apparatus for occlusion culling of graphic objects 审中-公开
    图形对象遮挡剔除的方法和装置

    公开(公告)号:US20060209065A1

    公开(公告)日:2006-09-21

    申请号:US11298167

    申请日:2005-12-08

    IPC分类号: G06T15/40

    CPC分类号: G06T15/40

    摘要: A method of occlusion culling of graphic objects, comprising the steps of storing a first mask and one or more depth values associated with areas inside and outside the mask for a pre-defined region, and evaluating the visibility of the primitive covering the same region, wherein visibility evaluation begins after the computation of the coverage mask of the primitive in the region, and the computation of one or more depth values representing the pixels of the primitive. The method of the present invention is a real-time method of generating per-region coverage mask and associated Z values after the second primitive is rendered in the same region, which can maximize the bandwidth savings for Z read for both overlapping and non-overlapping primitives, with different relations between their depth values.

    摘要翻译: 一种图形对象的遮挡剔除方法,包括以下步骤:存储第一掩码和与掩模内部和外部的区域相关联的一个或多个深度值用于预定义区域,以及评估覆盖相同区域的图元的可视性, 其中在计算区域中的原语的覆盖掩码之后开始可视性评估,以及计算表示图元的像素的一个或多个深度值。 本发明的方法是在将第二原语呈现在相同区域中之后生成每区域覆盖掩码和相关联的Z值的实时方法,这可以使重叠和非重叠的Z读取的带宽节省最大化 原始图像,其深度值之间具有不同的关系。

    Multi-resolution depth buffer
    2.
    发明授权
    Multi-resolution depth buffer 失效
    多分辨深度缓冲区

    公开(公告)号:US06677945B2

    公开(公告)日:2004-01-13

    申请号:US09839247

    申请日:2001-04-20

    IPC分类号: G06T1540

    CPC分类号: G06T15/405

    摘要: The present invention provides a system and method for eliminating hidden surfaces in 3D graphics that improves rendering performance by decreasing the size of the data stored to or retrieved from the depth buffer when the distance from the camera to the pixel on the surface of the primitive is further than the threshold distance. The threshold distance from the camera is defined such that for such pixels the precision of a linear or quazi-linear depth buffer with a decreased data size is the same as or higher than the precision of a non-linear depth buffer with an original data size. The invention improves the usefulness of linear and quasi-linear depth buffers for 3D applications optimized for non-linear depth buffers. The present invention additionally affords a method for selecting the size of data to be read from the depth buffer before new depth values are computed for the same pixels.

    摘要翻译: 本发明提供了一种用于消除3D图形中的隐藏表面的系统和方法,其中,当从相机到原始表面上的像素的距离为距离时,通过减小存储到深度缓冲器中或从深度缓冲器检索的数据的大小来提高渲染性能 超过阈值距离。 定义与摄像机的阈值距离,使得对于这样的像素,具有减小的数据大小的线性或奇数线性深度缓冲器的精度与具有原始数据大小的非线性深度缓冲器的精度相同或更高 。 本发明改进了针对非线性深度缓冲器优化的3D应用的线性和准线性深度缓冲器的有用性。 本发明另外提供一种用于在为相同像素计算新的深度值之前从深度缓冲器中选择要读取的数据的大小的方法。

    Floating-point complementary depth buffer
    3.
    发明授权
    Floating-point complementary depth buffer 失效
    浮点互补深度缓冲区

    公开(公告)号:US06453065B1

    公开(公告)日:2002-09-17

    申请号:US09778355

    申请日:2001-02-06

    IPC分类号: G06K900

    CPC分类号: G06K9/00 G06T15/405

    摘要: A method for evaluating the depth of a pixel in a scene, the scene enclosed in a view volume, the scene to be rendered from a camera position, the view volume having a near and a far plane, includes calculating a depth value for a pixel in the scene, the depth value being generated by a depth function of view distance within the view volume from the camera position, and storing the depth value in a floating-point format, the floating-point format including a mantissa and exponent, where, as the distance of the pixel to the far plane decreases, the absolute magnitude of the depth value generated by the depth function approaches the minimum non-negative number representable by the floating-point format.

    摘要翻译: 一种用于评估场景中的像素的深度,包含在视图体中的场景,从相机位置呈现的场景,具有近距离和远平面的视野体的方法,包括:计算像素的深度值 在场景中,深度值是通过从摄像机位置观看体积内的观看距离的深度函数产生的,并且将深度值以浮点格式存储,该浮点格式包括尾数和指数, 随着像素到远平面的距离减小,深度函数产生的深度值的绝对值接近浮点格式可表示的最小非负数。

    Floating-point complementary depth buffer
    4.
    发明授权
    Floating-point complementary depth buffer 失效
    浮点互补深度缓冲区

    公开(公告)号:US06285779B1

    公开(公告)日:2001-09-04

    申请号:US09365685

    申请日:1999-08-02

    IPC分类号: G06K900

    CPC分类号: G06K9/00 G06T15/405

    摘要: A method for evaluating the depth of a pixel in a scene, the scene enclosed in a view volume, the scene to be rendered from a camera position, the view volume having a near and a far plane, includes calculating a depth value for a pixel in the scene, the depth value being generated by a depth function of view distance within the view volume from the camera position, and storing the depth value in a floating-point format, the floating-point format including a mantissa and exponent, where, as the distance of the pixel to the far plane decreases, the absolute magnitude of the depth value generated by the depth function approaches the minimum non-negative number representable by the floating-point format.

    摘要翻译: 一种用于评估场景中的像素的深度,包含在视图体中的场景,从相机位置呈现的场景,具有近距离和远平面的视野体的方法,包括:计算像素的深度值 在场景中,深度值是通过从摄像机位置观看体积内的观看距离的深度函数产生的,并且将深度值以浮点格式存储,该浮点格式包括尾数和指数, 随着像素到远平面的距离减小,深度函数产生的深度值的绝对值接近浮点格式可表示的最小非负数。

    System and method for clearing depth and color buffers in a real-time graphics rendering system
    5.
    发明授权
    System and method for clearing depth and color buffers in a real-time graphics rendering system 失效
    在实时图形渲染系统中清除深度和色彩缓冲区的系统和方法

    公开(公告)号:US06982713B2

    公开(公告)日:2006-01-03

    申请号:US10341842

    申请日:2003-01-13

    IPC分类号: G06T15/40

    CPC分类号: G06T15/405

    摘要: A method and system for clearing depth and color buffers in a real time graphics rendering system 10. The method and system are able to improve both depth and color buffer clearing. The method and system may utilize a frame flag, a depth clearing module, and a fast color and frame flag clearing module. The system assigns a frame flag to each pixel, which is used to determine whether the current Z value for the pixel is valid. The frame flag may be attached to Z value in the depth buffer. Instead of filling entire depth and color buffers with background values, the system only fills the holes that were not drawn in the previous frame. The fast color and frame flag clearing module traverses a rectangular area, tile by tile, where a tile is a block of pixels, to determine whether each pixel is background by checking the frame flags that are read from the depth buffer. If at least one pixel of a tile is background, the module updates those pixels' color with background color by sending requests to memory interface.

    摘要翻译: 一种用于清除实时图形渲染系统10中的深度和色彩缓冲器的方法和系统。 该方法和系统能够改善深度和色彩缓冲清除。 该方法和系统可以利用帧标志,深度清除模块和快速颜色和帧标志清除模块。 系统为每个像素分配帧标志,用于确定像素的当前Z值是否有效。 帧标记可以附加到深度缓冲器中的Z值。 而不是使用背景值填充整个深度和颜色缓冲区,系统只填充未在前一帧中绘制的孔。 快速颜色和帧标志清除模块通过检查从深度缓冲器读取的帧标志来遍历矩形区域,瓦片,其中瓦片是像素块,以确定每个像素是否是背景。 如果瓦片的至少一个像素是背景,则模块通过向存储器接口发送请求来更新这些像素具有背景颜色的颜色。

    Out-of-order command execution with sliding windows to maintain completion statuses

    公开(公告)号:US10241799B2

    公开(公告)日:2019-03-26

    申请号:US12837600

    申请日:2010-07-16

    IPC分类号: G06F9/30 G06F9/38 G06T1/20

    摘要: Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.

    Multi-threaded processor with deferred thread output control
    7.
    发明授权
    Multi-threaded processor with deferred thread output control 有权
    具有延迟线程输出控制的多线程处理器

    公开(公告)号:US08869147B2

    公开(公告)日:2014-10-21

    申请号:US11445100

    申请日:2006-05-31

    摘要: A multi-threaded processor is provided that internally reorders output threads thereby avoiding the need for an external output reorder buffer. The multi-threaded processor writes its thread results back to an internal memory buffer to guarantee that thread results are outputted in the same order in which the threads are received. A thread scheduler within the multi-threaded processor manages thread ordering control to avoid the need for an external reorder buffer. A compiler for the multi-threaded processor converts instructions that would normally send processed results directly to an external reorder buffer so that the processed thread results are instead sent to the internal memory buffer of the multi-threaded processor.

    摘要翻译: 提供一种多线程处理器,其内部重新排序输出线程,从而避免需要外部输出重排序缓冲器。 多线程处理器将其线程结果写回内部存储器缓冲区,以保证以与接收线程相同的顺序输出线程结果。 多线程处理器内的线程调度器管理线程排序控制,以避免需要外部重排序缓冲区。 用于多线程处理器的编译器将通常将处理结果直接发送到外部重排序缓冲器的指令转换成经处理的线程结果而不是发送到多线程处理器的内部存储器缓冲区。

    Unified virtual addressed register file
    8.
    发明授权
    Unified virtual addressed register file 有权
    统一的虚拟寻址寄存器文件

    公开(公告)号:US08766996B2

    公开(公告)日:2014-07-01

    申请号:US11472701

    申请日:2006-06-21

    IPC分类号: G09G5/36

    摘要: A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

    摘要翻译: 提供了多线程处理器,例如着色器处理器,具有由多个线程共享的内部统一存储器空间,并且根据需要动态分配给线程。 映射表将虚拟寄存器映射到统一存储空间中的可用内部地址,以便线程寄存器可以存储在连续或不连续的存储器地址中。 虚拟寄存器的动态大小允许根据线程寄存器中数据的类型和大小灵活分配统一存储空间。 另一个特征提供了用于将统计存储器空间中的图形数据存储以改善从存储器空间获取和存储操作的有效方法。 特别地,线程中的四个像素的像素数据被存储在具有独立输入/输出端口的四个存储器件中,这些存储器件允许以单个时钟周期读取四个像素进行处理。

    Multi-stage tessellation for graphics rendering
    9.
    发明授权
    Multi-stage tessellation for graphics rendering 有权
    图形渲染的多阶段镶嵌

    公开(公告)号:US08643644B2

    公开(公告)日:2014-02-04

    申请号:US12052628

    申请日:2008-03-20

    IPC分类号: G06T15/30 G06T17/20

    CPC分类号: G06T11/203

    摘要: This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.

    摘要翻译: 本公开描述了用于在图形渲染期间细分曲线的多阶段镶嵌技术。 特别地,第一细分阶段将曲线细分为第一组线段,每组线段表示曲线的一部分。 第二细分阶段进一步将由第一组的每个线段表示的曲线的部分细分为更精细地表示曲线形状的附加线段。 以这种方式,在第一细分阶段之后仅由一个线段表示的曲线的每个部分在第二细分阶段之后被多于一个线段表示。 在一些情况下,可以执行多于两个的细分阶段来细分曲线。

    Shader compile system and method
    10.
    发明授权
    Shader compile system and method 有权
    着色器编译系统和方法

    公开(公告)号:US08495602B2

    公开(公告)日:2013-07-23

    申请号:US11864563

    申请日:2007-09-28

    IPC分类号: G06F9/45

    CPC分类号: G06T15/50 G06F8/41

    摘要: The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.

    摘要翻译: 本公开包括着色器编译器系统和方法。 在一个实施例中,着色器编译器包括将具有向量表示的指令转换为统一指令表示的解码器。 着色器编译器还包括将具有统一指令表示的指令转换为处理器可执行指令的编码器。