公开(公告)号：US20090237401A1

公开(公告)日：2009-09-24

申请号：US12052628

申请日：2008-03-20

申请人： Jian Wei ,  Guofang Jiao ,  Ning Bi ,  Chehui Wu

发明人： Jian Wei ,  Guofang Jiao ,  Ning Bi ,  Chehui Wu

IPC分类号： G06T17/00

CPC分类号： G06T11/203

摘要： This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.

摘要翻译： 本公开描述了用于在图形渲染期间细分曲线的多阶段镶嵌技术。 特别地，第一细分阶段将曲线细分为第一组线段，每组线段表示曲线的一部分。 第二细分阶段进一步将由第一组的每个线段表示的曲线的部分细分为更精细地表示曲线形状的附加线段。 以这种方式，在第一细分阶段之后仅由一个线段表示的曲线的每个部分在第二细分阶段之后被多于一个线段表示。 在一些情况下，可以执行多于两个的细分阶段来细分曲线。

公开(公告)号：US08643644B2

公开(公告)日：2014-02-04

申请号：US12052628

申请日：2008-03-20

申请人： Jian Wei ,  Guofang Jiao ,  Ning Bi ,  Chehui Wu

发明人： Jian Wei ,  Guofang Jiao ,  Ning Bi ,  Chehui Wu

IPC分类号： G06T15/30 ,  G06T17/20

CPC分类号： G06T11/203

摘要： This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.

摘要翻译： 本公开描述了用于在图形渲染期间细分曲线的多阶段镶嵌技术。 特别地，第一细分阶段将曲线细分为第一组线段，每组线段表示曲线的一部分。 第二细分阶段进一步将由第一组的每个线段表示的曲线的部分细分为更精细地表示曲线形状的附加线段。 以这种方式，在第一细分阶段之后仅由一个线段表示的曲线的每个部分在第二细分阶段之后被多于一个线段表示。 在一些情况下，可以执行多于两个的细分阶段来细分曲线。

公开(公告)号：US08200917B2

公开(公告)日：2012-06-12

申请号：US11862063

申请日：2007-09-26

申请人： Chun Yu ,  Guofang Jiao ,  Jian Wei

发明人： Chun Yu ,  Guofang Jiao ,  Jian Wei

IPC分类号： G06F12/14

CPC分类号： G06F12/0844 ,  G06F12/0842 ,  Y02D10/13

摘要： The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line.

摘要翻译： 本公开涉及用于锁定和解锁包含在多媒体处理器内的高速缓存中的高速缓存线的技术，该多媒体处理器使用对存储在外部存储器或嵌入式存储器中的数据进行批量读取和写入请求来执行读取 - 修改 - 写入功能。 这些技术可以包括在包含在高速缓存行的一部分中的数据的一批读取请求中接收读取请求，并响应于读取请求设置与该部分相关联的锁定位。 当锁定位设置时，批量读取请求中的其他读取请求无法访问高速缓存行的该部分中的数据。 响应于一批写请求中的写请求，锁定位可能未设置，以更新先前从高速缓存行的该部分读出的数据。

公开(公告)号：US20090083497A1

公开(公告)日：2009-03-26

申请号：US11862063

申请日：2007-09-26

申请人： Chun Yu ,  Guofang Jiao ,  Jian Wei

发明人： Chun Yu ,  Guofang Jiao ,  Jian Wei

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0844 ,  G06F12/0842 ,  Y02D10/13

摘要： The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line.

摘要翻译： 本公开涉及用于锁定和解锁包含在多媒体处理器内的高速缓存中的高速缓存线的技术，该多媒体处理器使用对存储在外部存储器或嵌入式存储器中的数据进行批量读取和写入请求来执行读取 - 修改 - 写入功能。 这些技术可以包括在包含在高速缓存行的一部分中的数据的一批读取请求中接收读取请求，并响应于读取请求设置与该部分相关联的锁定位。 当锁定位设置时，批量读取请求中的其他读取请求无法访问高速缓存行的该部分中的数据。 响应于一批写请求中的写请求，锁定位可能未设置，以更新先前从高速缓存行的该部分读出的数据。

公开(公告)号：US10241799B2

公开(公告)日：2019-03-26

申请号：US12837600

申请日：2010-07-16

申请人： Alexei V. Bourd ,  Guofang Jiao

发明人： Alexei V. Bourd ,  Guofang Jiao

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06T1/20

摘要： Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.

公开(公告)号：US08869147B2

公开(公告)日：2014-10-21

申请号：US11445100

申请日：2006-05-31

申请人： Yun Du ,  Guofang Jiao ,  Chun Yu

发明人： Yun Du ,  Guofang Jiao ,  Chun Yu

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/4881 ,  G06F9/30123 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  Y02D10/24

摘要： A multi-threaded processor is provided that internally reorders output threads thereby avoiding the need for an external output reorder buffer. The multi-threaded processor writes its thread results back to an internal memory buffer to guarantee that thread results are outputted in the same order in which the threads are received. A thread scheduler within the multi-threaded processor manages thread ordering control to avoid the need for an external reorder buffer. A compiler for the multi-threaded processor converts instructions that would normally send processed results directly to an external reorder buffer so that the processed thread results are instead sent to the internal memory buffer of the multi-threaded processor.

摘要翻译： 提供一种多线程处理器，其内部重新排序输出线程，从而避免需要外部输出重排序缓冲器。 多线程处理器将其线程结果写回内部存储器缓冲区，以保证以与接收线程相同的顺序输出线程结果。 多线程处理器内的线程调度器管理线程排序控制，以避免需要外部重排序缓冲区。 用于多线程处理器的编译器将通常将处理结果直接发送到外部重排序缓冲器的指令转换成经处理的线程结果而不是发送到多线程处理器的内部存储器缓冲区。

公开(公告)号：US08766996B2

公开(公告)日：2014-07-01

申请号：US11472701

申请日：2006-06-21

申请人： Yun Du ,  Guofang Jiao ,  Chun Yu ,  De Dzwo Hsu

发明人： Yun Du ,  Guofang Jiao ,  Chun Yu ,  De Dzwo Hsu

IPC分类号： G09G5/36

CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/384 ,  G06T15/005

摘要： A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

摘要翻译： 提供了多线程处理器，例如着色器处理器，具有由多个线程共享的内部统一存储器空间，并且根据需要动态分配给线程。 映射表将虚拟寄存器映射到统一存储空间中的可用内部地址，以便线程寄存器可以存储在连续或不连续的存储器地址中。 虚拟寄存器的动态大小允许根据线程寄存器中数据的类型和大小灵活分配统一存储空间。 另一个特征提供了用于将统计存储器空间中的图形数据存储以改善从存储器空间获取和存储操作的有效方法。 特别地，线程中的四个像素的像素数据被存储在具有独立输入/输出端口的四个存储器件中，这些存储器件允许以单个时钟周期读取四个像素进行处理。

公开(公告)号：US08495602B2

公开(公告)日：2013-07-23

申请号：US11864563

申请日：2007-09-28

申请人： Lin Chen ,  Guofang Jiao ,  Chihong Zhang ,  Junhong Sun

发明人： Lin Chen ,  Guofang Jiao ,  Chihong Zhang ,  Junhong Sun

IPC分类号： G06F9/45

CPC分类号： G06T15/50 ,  G06F8/41

摘要： The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.

摘要翻译： 本公开包括着色器编译器系统和方法。 在一个实施例中，着色器编译器包括将具有向量表示的指令转换为统一指令表示的解码器。 着色器编译器还包括将具有统一指令表示的指令转换为处理器可执行指令的编码器。

公开(公告)号：US08345053B2

公开(公告)日：2013-01-01

申请号：US11533880

申请日：2006-09-21

申请人： Guofang Jiao ,  Yun Du ,  Chun Yu

发明人： Guofang Jiao ,  Yun Du ,  Chun Yu

IPC分类号： G06F15/80 ,  G06F15/00 ,  G06T1/00

CPC分类号： G06T15/005

摘要： A graphics processor capable of parallel scheduling and execution of multiple threads, and techniques for achieving parallel scheduling and execution, are described. The graphics processor may include multiple hardware units and a scheduler. The hardware units are operable in parallel, with each hardware unit supporting a respective set of operations. The hardware units may include an ALU core, an elementary function core, a logic core, a texture sampler, a load control unit, some other hardware unit, or a combination thereof. The scheduler dispatches instructions for multiple threads to the hardware units concurrently. The graphics processor may further include an instruction cache to store instructions for threads and register banks to store data. The instruction cache and register banks may be shared by the hardware units.

摘要翻译： 描述了能够并行调度和执行多个线程的图形处理器以及用于实现并行调度和执行的技术。 图形处理器可以包括多个硬件单元和调度器。 硬件单元可并行操作，每个硬件单元支持相应的一组操作。 硬件单元可以包括ALU核，基本功能核心，逻辑核心，纹理采样器，负载控制单元，一些其他硬件单元或其组合。 调度器将多个线程的指令同时分配到硬件单元。 图形处理器还可以包括指令高速缓存以存储线程和寄存器组以存储数据的指令。 指令高速缓存和寄存器组可以由硬件单元共享。

公开(公告)号：US08022958B2

公开(公告)日：2011-09-20

申请号：US11696665

申请日：2007-04-04

申请人： Guofang Jiao ,  Lingjun Chen ,  Yun Du

发明人： Guofang Jiao ,  Lingjun Chen ,  Yun Du

IPC分类号： G06T15/00 ,  G06T15/50 ,  G09G5/36

CPC分类号： G06T15/00

摘要： This disclosure describes techniques of loading batch commands into a graphics processing unit (GPU). As described herein, a GPU driver for the GPU identifies one or more graphics processing objects to be used by the GPU in order to render a batch of graphics primitives. The GPU driver may insert indexes associated with the identified graphics processing objects into a batch command. The GPU driver may then issue the batch command to the GPU. The GPU may use the indexes in the batch command to retrieve the graphics processing objects from memory. After retrieving the graphics processing objects from memory, the GPU may use the graphics processing objects to render the batch of graphics primitives.

摘要翻译： 本公开描述了将批处理命令加载到图形处理单元（GPU）中的技术。 如本文所述，用于GPU的GPU驱动器识别要由GPU使用的一个或多个图形处理对象，以便呈现一批图形基元。 GPU驱动程序可以将与所识别的图形处理对象相关联的索引插入到批处理命令中。 然后，GPU驱动程序可以向GPU发出批处理命令。 GPU可以使用批处理命令中的索引从内存中检索图形处理对象。 在从存储器检索图形处理对象之后，GPU可以使用图形处理对象来渲染批量的图形基元。