公开(公告)号：US12022738B2

公开(公告)日：2024-06-25

申请号：US17270151

申请日：2019-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Sarin Deshpande ,  Kerry Nagel ,  Santosh Karre

IPC: H10N50/01 ,  H10N50/80 ,  H01F10/32 ,  H10B61/00

CPC classification number: H10N50/01 ,  H10N50/80 ,  H01F10/3254 ,  H01F10/3272 ,  H10B61/00

Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.