公开(公告)号：US07038936B2

公开(公告)日：2006-05-02

申请号：US10503459

申请日：2003-01-20

申请人： Evert Seevinck ,  Alain Michel Marie Thijs ,  Patrick Van De Steeg ,  Maurits Mario Nicolaas Storms

发明人： Evert Seevinck ,  Alain Michel Marie Thijs ,  Patrick Van De Steeg ,  Maurits Mario Nicolaas Storms

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C11/419

摘要： A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can be connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

摘要翻译： 读取电路包括第一和第二共源共栅电路以及第一和第二电流镜。 第一级联电路可以连接到存储器单元的位线，并且第二级联电路可以连接到参考单元的参考位线。 第一和第二共源共栅电路的第一输出端分别连接到第一和第二电流镜的第一端。 第一和第二共源共栅电路的第二输出端分别连接到第二和第一电流镜的第二端。 三态缓冲器耦合在第一和第二电流镜的第二端之间，所述缓冲器具有位反转能力。

公开(公告)号：US20050270833A1

公开(公告)日：2005-12-08

申请号：US10503459

申请日：2003-01-20

申请人： Evert Seevinck ,  Alain Thijs ,  Patrick Van De Steeg ,  Maurits Storms

发明人： Evert Seevinck ,  Alain Thijs ,  Patrick Van De Steeg ,  Maurits Storms

IPC分类号： G11C17/18 ,  G11C7/06 ,  G11C11/409 ,  G11C11/419 ,  G11C16/28 ,  G11C11/34

CPC分类号： G11C7/062 ,  G11C11/419

摘要： A reading circuit comprises a first and second cascode circuit and a first and second current mirror. The first cascode circuit can connected to a bit line of a memory cell and the second cascode circuit can be connected to a reference bit line of a reference cell. The first output terminals of the first and second cascode circuits are connected to first terminals of the first and second current mirrors, respectively. The second output terminals of the first and second cascode circuits are connected to the second terminals of the second and first current mirrors, respectively. A tri-state buffer is coupled between the second terminals of the first and second current mirrors said buffer having bit invert capabilities.

摘要翻译： 读取电路包括第一和第二共源共栅电路以及第一和第二电流镜。 第一级联电路可以连接到存储器单元的位线，并且第二共源共栅电路可以连接到参考单元的参考位线。 第一和第二共源共栅电路的第一输出端分别连接到第一和第二电流镜的第一端。 第一和第二共源共栅电路的第二输出端分别连接到第二和第一电流镜的第二端。 三态缓冲器耦合在第一和第二电流镜的第二端之间，所述缓冲器具有位反转能力。