公开(公告)号：US20040012414A1

公开(公告)日：2004-01-22

申请号：US10199620

申请日：2002-07-19

申请人： Exar Corporation

发明人： Shin Chung Chen ,  Roubik Gregorian ,  Mir Bahram Ghaderi ,  Vincent Sing Tso

IPC分类号： H03D003/00

CPC分类号： H03L7/089 ,  H03L7/085 ,  H04L7/033

摘要： A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

摘要翻译： 通过增加Hogge型相位检测器的泵浦和抽吸脉冲的脉冲宽度，而不分时钟来处理更快的时钟速度的机制。 特别地，NRZ数据流被分成两个，这两个是通过两个触发器系列提供的交错数据流。 通过将异或门分别连接到两个触发器系列以产生泵浦和抽吸脉冲，可以通过两个不同的使用的替代转换（上和下）来实现转换之间更长的时间 系列触发器。 此外，提供延迟电路以补偿触发器的时钟到数据输出延迟。

公开(公告)号：US20030190001A1

公开(公告)日：2003-10-09

申请号：US10118661

申请日：2002-04-08

申请人： Exar Corporation

发明人： Roubik Gregorian ,  Mir Bahram Ghaderi ,  James Ban Ho ,  Vincent Sing Tso

IPC分类号： H04L007/02

CPC分类号： H04L7/033 ,  H03L7/0891 ,  H03L7/091

摘要： A converting circuit which converts RZ data into intermeidate NRZ data. The intermediate NRZ data is then sampled to detect a phase of the intermediate NRZ data, which corresponds to the phase of the RZ data. In a preferred embodiment, the converting circuit is incorporated in a modified Hogge NRZ phase detector. A toggle flip-flop is placed in front of the Hogge phase detector. Since the toggle flip-flop is triggered by the leading edge of the RZ pulse, it essentially converts the RZ data into intermediate NRZ data. An exclusive-OR gate samples two different output stages of the Hogge NRZ phase detector, with the output stages being separated by an interim stage to provide a clock delay. The output of the exclusive-OR gate is an intermediate NRZ signal that corresponds to the input RZ data stream, which can then be sampled. The exclusive-OR gates inside the Hogge phase detector are used, as in the Hogge phase detector, to produce the up and down signals provided to a charge pump that is part of a PLL. The insertion of the toggle flip-flop allows these same exclusive-OR gates to perform the same function in the present invention.

摘要翻译： A转换电路，将RZ数据转换成中间NRZ数据。 然后对中间NRZ数据进行采样以检测对应于RZ数据的相位的中间NRZ数据的相位。 在优选实施例中，转换电路并入修改后的Hogge NRZ相位检测器中。 开关触发器位于Hogge相位检测器的前面。 由于切换触发器由RZ脉冲的前沿触发，所以它基本上将RZ数据转换成中间NRZ数据。 异或门对Hogge NRZ相位检测器的两个不同输出级进行采样，输出级由中间级分隔，以提供时钟延迟。 异或门的输出是对应于输入RZ数据流的中间NRZ信号，然后可以对其进行采样。 使用Hogge相位检测器内的异或门，如在霍格相位检测器中，产生提供给作为PLL一部分的电荷泵的上下信号。 切换触发器的插入允许这些相同的异或门在本发明中执行相同的功能。