公开(公告)号：US11023023B2

公开(公告)日：2021-06-01

申请号：US16709021

申请日：2019-12-10

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Kun-Hua Huang ,  Chang-Chin Chung ,  Kun-Chih Chen

IPC: G06F1/24 ,  G06F13/42 ,  G06F1/04 ,  H03K19/20

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

公开(公告)号：US10423386B1

公开(公告)日：2019-09-24

申请号：US16012392

申请日：2018-06-19

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chang-Chin Chung ,  Shen-Chang Wang

IPC: G06F5/10 ,  G11C8/18 ,  G11C7/10

Abstract: A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.