公开(公告)号：US20230099269A1

公开(公告)日：2023-03-30

申请号：US17565503

申请日：2021-12-30

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar JAIN ,  Chi-Yeu CHAO

IPC: G06F1/10 ,  G06F1/12 ,  G06F1/08

Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.