公开(公告)号：US20230099269A1

公开(公告)日：2023-03-30

申请号：US17565503

申请日：2021-12-30

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar JAIN ,  Chi-Yeu CHAO

IPC: G06F1/10 ,  G06F1/12 ,  G06F1/08

Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

公开(公告)号：US20230208459A1

公开(公告)日：2023-06-29

申请号：US17575664

申请日：2022-01-14

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar JAIN

IPC: H04B1/10 ,  H03K5/24 ,  H03K19/20

CPC classification number: H04B1/1018 ,  H03K5/24 ,  H03K19/20

Abstract: A serial signal detector and a differential signal detection method are provided. The serial signal detector includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal, including a first shifted signal and a second shifted signal. The voltage comparison module includes a first comparator and a second comparator. Based on the first shifted signal, the second shifted signal, and a voltage threshold, the first and the second comparators respectively generate a first and a second comparison signals. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first and the second comparison signals and generates a filtered and converted pulse accordingly. The controllable logic gate and the capacitor jointly perform a preliminary filtering operation to the filtered and converted pulse while the logic operation is being performed.