公开(公告)号：US09466357B2

公开(公告)日：2016-10-11

申请号：US14602739

申请日：2015-01-22

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Ching-Te Chuang ,  Chien-Yu Lu ,  Ming-Ching Zheng ,  Ming-Hsien Tu

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract translation: 提供了一种用于减轻包括第一和第二放电控制路径的写干扰的电路并将其应用于双端口SRAM。 第一放电控制路径连接到第二端口和第一端口的位线，以及第一控制线。 第二放电控制路径连接到第二端口和第一端口与第一控制线的反位线。 当第二端口和第一端口的位线分别处于高电平电压和低电平电压，并且第一控制线路工作时，产生第一放电电流。 当第二端口和第一端口的反位线分别处于高电平电压和低电平电压，并且第一控制线工作时，产生第二放电电流。

公开(公告)号：US20160027500A1

公开(公告)日：2016-01-28

申请号：US14602739

申请日：2015-01-22

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Ching-Te Chuang ,  Chien-Yu Lu ,  Ming-Ching Zheng ,  Ming-Hsien Tu

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.

Abstract translation: 提供了一种用于减轻包括第一和第二放电控制路径的写干扰的电路并将其应用于双端口SRAM。 第一放电控制路径连接到第二端口和第一端口的位线，以及第一控制线。 第二放电控制路径连接到第二端口和第一端口与第一控制线的反位线。 当第二端口和第一端口的位线分别处于高电平电压和低电平电压，并且第一控制线路工作时，产生第一放电电流。 当第二端口和第一端口的反位线分别处于高电平电压和低电平电压，并且第一控制线工作时，产生第二放电电流。