公开(公告)号：US20200272536A1

公开(公告)日：2020-08-27

申请号：US16429618

申请日：2019-06-03

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Shan-Tai CHEN ,  Jian-Guo CHEN ,  Chun-Yuan LAI

IPC: G06F11/10 ,  G06F9/4401 ,  G06F12/02 ,  H04L9/06

Abstract: A method of executing an initial program load in an electronic device is provided. The electronic device includes a chip. The chip is connected with a storage device. The method includes the following steps. First, checking data and a characteristic value are read from the storage device. Then, an algorithm parameter is acquired from the checking data. Then, the checking data and the characteristic value are verified according to a specified checking algorithm and the algorithm parameter. If a result of the specified checking algorithm passes, a boot code is executed. If the result of the specified checking algorithm fails, a notification signal is issued.

公开(公告)号：US20230351055A1

公开(公告)日：2023-11-02

申请号：US17899653

申请日：2022-08-31

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chun-Yuan LAI

IPC: G06F21/72 ,  H04L9/14 ,  H04L9/08 ,  H04L9/06 ,  G06F21/57

CPC classification number: G06F21/72 ,  H04L9/14 ,  H04L9/0894 ,  H04L9/0618 ,  G06F21/575 ,  G06F2221/034

Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

公开(公告)号：US20240330225A1

公开(公告)日：2024-10-03

申请号：US18432412

申请日：2024-02-05

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chun-Yuan LAI

IPC: G06F13/40

CPC classification number: G06F13/4068

Abstract: A physical layer module and a network module are provided. The network module includes the physical layer module and a media access control module. The physical layer module includes a group decoder, an input selection module, and a device module. The group decoder decodes a common input data signal generated according to a management data input/output signal to generate a group selection signal. The input selection module includes X input circuits being classified into M groups. The X input circuits generate X device input data according to the common input data signal and the group selection signal. The device module includes K physical layer devices classified into M groups. The K physical devices receive X device input data from the X input circuits. An m-th group corresponds to at least one input circuit and N[m] physical layer devices.

公开(公告)号：US20200303948A1

公开(公告)日：2020-09-24

申请号：US16459680

申请日：2019-07-02

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chun-Yuan LAI

IPC: H02J9/06

Abstract: A circuit system includes a first power source, a second power source, a first interface circuit, a second interface circuit and an isolation circuit. The first interface circuit is included in a first power domain. The second interface circuit is includes in a second power domain. The bus signal group from the first interface circuit is transmitted to the second interface circuit through the isolation circuit. In a power-saving mode, the bus signal group in a floating state can be effectively isolated by the isolation circuit. If a sudden power interruption event occurs when the circuit system is in the normal working mode, the bus signal group in the floating state is isolated by the isolation circuit. Moreover, the isolation circuit is capable of filtering off the incomplete transaction data, and thus the second interface circuit is not suffered from malfunction.