公开(公告)号：US20180046392A1

公开(公告)日：2018-02-15

申请号：US15236459

申请日：2016-08-14

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： VIVEK SINGH ,  AMAN DAHIYA ,  NAVDEEP SINGH GILL ,  PIYUSH K. UPADHYAY

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048

Abstract: A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. The data transaction is either a read transaction or a write transaction. The system includes an input and output interface in communication with the master for receiving a data transaction request, an identifying unit that identifies a type of the data transaction, a control unit that selectively enables at least one of the first and second cuts based on the data transaction type, and a data processing unit that processes data to be read from or written to the enabled cut based on the data transaction type.