公开(公告)号：US10180925B2

公开(公告)日：2019-01-15

申请号：US15081944

申请日：2016-03-28

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Rajan Srivastava ,  Girraj K. Agrawal

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/16

Abstract: An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.

公开(公告)号：US09772963B2

公开(公告)日：2017-09-26

申请号：US14809269

申请日：2015-07-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Priyanka Jain ,  Girraj K. Agrawal ,  Rajan Srivastava

IPC: G06F13/00 ,  G06F13/32 ,  G06F9/48

CPC classification number: G06F13/32 ,  G06F9/4825 ,  G06F9/4837

Abstract: An interrupt management system for managing multiple interrupts includes a timer and an interrupt management sub-system. The interrupt management sub-system receives first and second interrupts, determines the first interrupt to be a real-time interrupt and the second interrupt to be a non-real-time interrupt, initializes the timer for a predetermined time period on reception of the first interrupt, and determines whether the second interrupt is either a maskable or non-maskable interrupt. The interrupt management sub-system transmits the first interrupt to an interrupt controller, en-queues the second interrupt during the predetermined time period, and transmits the second interrupt to the interrupt controller after the predetermined time period when the second interrupt is a maskable interrupt. The interrupt management sub-system transmits the second interrupt to the interrupt controller during the predetermined time period when the second interrupt is a non-maskable interrupt.