公开(公告)号：US09360883B1

公开(公告)日：2016-06-07

申请号：US14835738

申请日：2015-08-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Arun Kumar Barman ,  Vivek Sharma

IPC: H03K17/00 ,  G06F1/08

CPC classification number: G06F1/08

Abstract: A fully digital glitch-free clock multiplexer includes a monitoring circuit that automatically switches to a newly selected clock, after a defined time period, from a currently selected clock, when the currently selected clock is absent. A maximum time limit is calculated based on a min and max clock frequency ratio. The monitoring circuit operates only when the clock is being switched. This provides flexibility to software to switch the clock any time whether or not the current clock is present, and prevents the system from hanging in the absence of the clock.

Abstract translation: 完全数字无故障的时钟多路复用器包括一个监视电路，当当前选择的时钟不存在时，监控电路在定义的时间段之后从当前选择的时钟自动切换到新选择的时钟。 基于最小和最大时钟频率比计算最大时限。 监控电路仅在时钟切换时才起作用。 这样，无论当前时钟是否存在，软件都可以随时更改时钟的灵活性，并且在没有时钟的情况下防止系统挂起。

公开(公告)号：US09891986B2

公开(公告)日：2018-02-13

申请号：US15006130

申请日：2016-01-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Nikhil Sharma ,  Rajesh Gupta ,  Vivek Sharma

IPC: G06F11/00 ,  G06F11/10 ,  G06F13/28 ,  G06F13/40 ,  G06F3/06 ,  G06F11/30

CPC classification number: G06F11/1016 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/068 ,  G06F11/3027 ,  G06F13/28 ,  G06F13/404 ,  G06F2201/81 ,  G06F2201/87

Abstract: A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. The protection code processing circuit generates and inserts a protection code into data to be written to the memory, and removes a protection code from data read from the memory. The system facilitates error checking without requiring modification of the channels (e.g., bus width) used to read and/or write data to memory.